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ZHCSA60C May 2012 – May 2015 PCM5100A , PCM5100A-Q1 , PCM5101A , PCM5101A-Q1 , PCM5102A , PCM5102A-Q1

PRODUCTION DATA.

封裝選項

機械數(shù)據(jù) (封裝 | 引腳)

PW|20
- MPDS362A

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

訂購信息

8 Specifications

8.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
Supply voltage	AVDD, CPVDD, DVDD	–0.3	3.9	V
Supply voltage	LDO with DVDD at 1.8 V	–0.3	2.25
Digital input voltage	DVDD at 1.8 V	–0.3	2.25
Digital input voltage	DVDD at 3.3 V	–0.3	3.9
Analog input voltage		–0.3	3.9
Operating junction temperature range		–40	130	°C
Storage temperature, T_stg		–65	150	°C

8.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±750	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions

				MIN	NOM	MAX	UNIT
AVDD	Analog power supply voltage range	Referenced to AGND⁽¹⁾	VCOM mode	3	3.3	3.46	V
AVDD	Analog power supply voltage range	Referenced to AGND⁽¹⁾	VREF mode	3.2	3.3	3.46	V
DVDD	Digital power supply voltage range	Referenced to DGND⁽¹⁾	1.8 V DVDD	1.65	1.8	1.95	V
DVDD	Digital power supply voltage range	Referenced to DGND⁽¹⁾	3.3 V DVDD	3.1	3.3	3.46	V
CPVDD	Charge pump supply voltage range	Referenced to CPGND⁽¹⁾		3.1	3.3	3.46	V
MCLK	Master clock frequency					50	MHz
LOL, LOR	Stereo line output load resistance			1	10		kΩ
C_LOUT	Digital output load capacitance				10		pF
T_J	Operating junction temperature range			–40		130	°C

(1) All grounds on board are tied together; they must not differ in voltage by more than 0.2 V max, for any combination of ground signals.

8.4 Thermal Information

THERMAL METRIC⁽¹⁾		PW	UNIT
THERMAL METRIC⁽¹⁾		20 PINS	UNIT
R_θJA	Junction-to-ambient thermal resistance	91.2	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	25.3
R_θJB	Junction-to-board thermal resistance	42
ψ_JT	Junction-to-top characterization parameter	1
ψ_JB	Junction-to-board characterization parameter	41.5
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	—

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

8.5 Electrical Characteristics

Q1 Automotive grade devices are specified for T_A = –40°C to 125°C. Consumer grade (non-Q1) devices are specified at T_A = 25°C. All devices in the family are characterized with AVDD = CPVDD = DVD = 3.3 V, f_S = 48 kHz, system clock = 512 f_S and 24-bit data unless otherwise noted.

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
	Resolution			16	24	32	Bits
Data Format (PCM Mode)
	Audio data bit length			16	24	32	Bits
f_S⁽⁷⁾	Sampling frequency			8		384	kHz
f_SCK	System clock frequency	Clock multiples: 64, 128, 192, 256, 384, 512, 768, 1024, 1152, 1536, 2048, or 3072				50	MHz
Digital Input/Output for non-Q1 Consumer Grade Devices
	Logic family: 3.3 V LVCMOS compatible
V_IH	Input logic level			0.7×DV_DD			V
V_IL	Input logic level					0.3×DV_DD	V
I_IH	Input logic current	V_IN = V_DD				10	µA
I_IL	Input logic current	V_IN = 0 V				–10	µA
V_OH	Output logic level	I_OH = –4 mA		0.8×DV_DD			V
V_OL	Output logic level	I_OL = 4 mA				0.22×DV_DD	V
	Logic family 1.8 V LVCMOS compatible
V_IH	Input logic level			0.7×DV_DD			V
V_IL	Input logic level					0.3×DV_DD	V
I_IH	Input logic current	V_IN = V_DD				10	µA
I_IL	Input logic current	V_IN = 0 V				–10	µA
V_OH	Output logic level	I_OH = –2 mA		0.8×DV_DD			V
V_OL	Output logic level	I_OL = 2 mA				0.22×DV_DD	V
Digital Input/Output for Q1 Automotive Grade Devices
	Logic family: 3.3 V LVCMOS compatible
V_IH	Input logic level			0.7×DV_DD			V
V_IL	Input logic level					0.3×DV_DD	V
I_IH	Input logic current	V_IN = V_DD				10	µA
I_IL	Input logic current	V_IN = 0 V				–10	µA
V_OH	Output logic level	I_OH = –4 mA		0.8×DV_DD			V
V_OL	Output logic level	I_OL = 4 mA				0.22×DV_DD	V
	Logic family 1.8 V LVCMOS compatible
V_IH	Input logic level			0.7×DV_DD			V
V_IL	Input logic level					0.3×DV_DD	V
I_IH	Input logic current	V_IN = V_DD				10	µA
I_IL	Input logic current	V_IN = 0 V				–10	µA
V_OH	Output logic level	I_OH = –2 mA		0.8×DV_DD			V
V_OL	Output logic level	I_OL = 2 mA				0.3×DV_DD	V
Dynamic Performance (PCM Mode)⁽¹⁾⁽²⁾
	THD+N at –1 dBFS⁽²⁾	f_S = 48 kHz	PCM5102A		–93	–83	dB
			PCM5101A		–92	–82
			PCM5100A		–90	–80
		f_S = 96 kHz and 192 kHz	PCM5102A		–93
			PCM5101A		–92
			PCM5100A		–90
	Dynamic range⁽²⁾	EIAJ, A-weighted, f_S = 48 kHz	PCM5102A	106	112
			PCM5101A	100	106
			PCM5100A	95	100
		EIAJ, A-weighted, f_S = 96 kHz and 192 kHz	PCM5102A		112
			PCM5101A		106
			PCM5100A		100
	Signal-to-noise ratio⁽²⁾	EIAJ, A-weighted, f_S = 48 kHz	PCM5102A		112
			PCM5101A		106
			PCM5100A		100
		EIAJ, A-weighted, f_S = 96 kHz and 192 kHz	PCM5102A		112
			PCM5101A		106
			PCM5100A		100
	Signal to noise ratio with analog mute⁽²⁾⁽³⁾	EIAJ, A-weighted, f_S = 48 kHz		113	123
	Signal to noise ratio with analog mute⁽²⁾⁽³⁾	EIAJ, A-weighted, f_S = 96 kHz and 192 kHz			123
	Channel separation	f_S = 48 kHz	PCM5102A	100	109
			PCM5101A	95	103
			PCM5100A	90	97
		f_S = 96 kHz	PCM5102A		109
			PCM5101A		103
			PCM5100A		97
		f_S = 192 kHz	PCM5102A		109
			PCM5101A		103
			PCM5100A		97
Analog Output
	Output voltage				2.1		V_RMS
	Gain error			–6	±2	6	% of FSR
	Gain error on Q1 Automotive Grade Devices			–7	±2	7	% of FSR
	Gain mismatch, channel-to-channel			–6	±2	6	% of FSR
	Gain mismatch, channel-to-channel on Q1 Devices			–6	±2	6	% of FSR
	PCM5100/1 bipolar zero error	At bipolar zero		–5	±1	5	mV
	PCM5102 Bipolar zero error	At bipolar zero		–2	±1	2	mV
	Load impedance			1			kΩ
Filter Characteristics–1: Normal
	Pass band					0.45f_S
	Stop band			0.55f_S
	Stop band attenuation			–60			dB
	Pass-band ripple					±0.02	dB
	Delay time				20t_S		s
Filter Characteristics–2: Low Latency
	Pass band					0.47f_S
	Stop band			0.55f_S
	Stop band attenuation			–52			dB
	Pass-band ripple					±0.0001	dB
	Delay time				3.5t_S		s
Power Supply Requirements
DV_DD	Digital supply voltage	Target DV_DD = 1.8 V		1.65	1.8	1.95	VDC
DV_DD	Digital supply voltage	Target DV_DD = 3.3 V		3	3.3	3.6	VDC
AV_DD	Analog supply voltage			3	3.3	3.6
CPV_DD	Charge-pump supply voltage			3	3.3	3.6
I_DD	DV_DD supply current at 1.8 V⁽⁴⁾	f_S = 48 kHz			7		mA
		f_S = 96 kHz			8
		f_S = 192 kHz			9
I_DD	DV_DD supply current at 1.8 V⁽⁵⁾	f_S = 48 kHz			7		mA
		f_S = 96 kHz			8
		f_S = 192 kHz			9
I_DD	DV_DD supply current at 1.8 V⁽⁶⁾	Standby			0.3		mA
I_DD	DV_DD supply current at 3.3 V⁽⁴⁾	f_S = 48 kHz			7	12	mA
		f_S = 96 kHz			8
		f_S = 192 kHz			9
I_DD	DV_DD supply current at 3.3 V⁽⁵⁾	f_S = 48 kHz			8	13	mA
		f_S = 96 kHz			9
		f_S = 192 kHz			10
I_DD	DV_DD supply current at 3.3 V⁽⁶⁾	Standby			0.5	0.8	mA
I_DD	AV_DD / CPV_DD supply current⁽⁴⁾	f_S = 48 kHz			11	16	mA
		f_S = 96 kHz			11
		f_S = 192 kHz			11
I_DD	AV_DD / CPV_DD supply current⁽⁵⁾	f_S = 48 kHz			22	32	mA
		f_S = 96 kHz			22
		f_S = 192 kHz			22
I_DD	AV_DD / CPV_DD supply current⁽⁶⁾	f_S = n/a			0.2	0.4	mA
	Power dissipation, DV_DD = 1.8 V⁽⁴⁾	f_S = 48 kHz			49	185	mW
		f_S = 96 kHz			51
		f_S = 192 kHz			53
	Power dissipation, DV_DD = 1.8 V⁽⁵⁾	f_S = 48 kHz			85	187	mW
		f_S = 96 kHz			87
		f_S = 192 kHz			89
	Power dissipation, DV_DD = 1.8 V⁽⁶⁾	f_S = n/a (Power Down Mode)			1		mW
	Power dissipation, DV_DD = 3.3 V⁽⁴⁾	f_S = 48 kHz			60	92.4	mW
		f_S = 96 kHz			63
		f_S = 192 kHz			66
	Power dissipation, DV_DD = 3.3 V⁽⁵⁾	f_S = 48 kHz			99	148.5	mW
		f_S = 96 kHz			102
		f_S = 192 kHz			106
	Power dissipation, DV_DD = 3.3 V⁽⁶⁾	f_S = n/a (Power Down Mode)			2	4	mW

(1) Filter condition: THD+N: 20-Hz HPF, 20-kHz AES17 LPF; Dynamic range: 20-Hz HPF, 20-kHz AES17 LPF; A-weighted signal-to-noise ratio: 20-Hz HPF, 20-kHz AES17 LPF; A-weighted channel separation: 20-Hz HPF, 20-kHz AES17 LPF. Analog performance specifications are measured using the System Two Cascade™ audio measurement system by Audio Precision™ in the RMS mode.

(2) Output load is 10 kΩ, with 470-Ω output resistor and a 2.2-nF shunt capacitor (see recommended output filter).

(3) Assert XSMT or both L-ch and R-ch PCM data are Bipolar Zero.

(4) Input is Bipolar Zero data.

(5) Input is 1 kHz –1 dBFS data.

(6) Power Down Mode

(7) One sample time is defined as the reciprocal of the sampling frequency. 1t_S = 1/f_S

8.6 Timing Requirements

Figure 1 shows the timing requirements for the system clock input. For optimal performance, use a clock source with low phase jitter and noise.

			MIN	MAX	UNIT
t_SCY	System clock pulse cycle time		20	1000	ns
t_SCKH	System clock pulse width, High	DVDD = 1.8 V	8		ns
t_SCKH	System clock pulse width, High	DVDD = 3.3 V	9		ns
t_SCKL	System clock pulse width, Low	DVDD = 1.8 V	8		ns
t_SCKL	System clock pulse width, Low	DVDD = 3.3 V	9		ns

PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1 f_pcm51xx_td_sck_req.gif

Figure 1. Timing Requirements for SCK Input

8.7 Timing Requirements, XSMT

		MIN	TYP	MAX	UNIT
t_r	Rise time			20	ns
t_f	Fall time			20	ns

PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1 f_pcm51xx_td_xsmt_soft_mute.gif

Figure 2. XSMT Timing for Soft Mute and Soft Un-Mute

8.8 Typical Characteristics

Q1 Automotive grade devices are specified for T_A = –40°C to 125°C. Consumer grade (non-Q1) devices are specified at T_A = 25°C, AV_DD = CPV_DD = DV_DD = 3.3 V, f_S = 48 kHz, system clock = 512 f_S and 24-bit data unless otherwise noted.