5 修訂歷史記錄

Changes from B Revision (January 2015) to C Revision

• Changed 簡(jiǎn)化系統(tǒng)圖Go
• Changed typical performance table to reflect part differences accurately Go
• Changed "Storage temperatures, T_stg" to "Operating junction temperature range at –40°C to 130°C"Go
• Changed "Storage temperature (Q1 devices) –40°C to 125°C" to "Storage temperatures, T_stg –65°C to 150°C"Go
• Updated ESD Data Go
• Changed the stereo line output load resistance MIN value in the Recommended Operating Conditions from "2 kΩ" to "1 kΩ"Go
• Changed the operating junction temperature range in the Recommended Operating Conditions from "MIN = –25°C MAX = 85°C" to "MIN = –40°C MAX = 130°C"Go
• Added "Q1 Automotive grade devices..." and "Consumer grade (non-Q1) devices..." to the condition statement in the Electrical CharacteristicsGo
• Changed "Gain error on Q1 Devices" to "Gain error on Q1 Automotive Grade Devices" in Electrical CharacteristicsGo
• Changed min/max bipolar offset error for PCM5xx2 to be ±2 mV Go
• Updated graph titles with device prefixGo
• Added "Q1 Automotive grade devices..." and "Consumer grade (non-Q1) devices..." to the condition statement in the Typical Characteristics graphs section.Go
• Changed "MCK" to "SCK" at the PLL Clock in the Functional Block DiagramGo
• Added details to Zero Data Detection about the default behavior of the device Go
• Added label "Mute Circuit" and ground symbols to pins DEMP and FMT in Figure 33 Go
• Added details about fast control of XSMT Go

Changes from A Revision (September 2012) to B Revision

• Added ESD 額定值表，詳細(xì) 說(shuō)明部分，應(yīng)用和實(shí)施部分，電源相關(guān)建議部分，器件和文檔支持部分以及機(jī)械、封裝和可訂購(gòu)信息Go
• Added 1.8V DVDD 電源項(xiàng)Go
• Changed 特性列表。Go
• Changed "Operating temperature range " to "Operating junction temperature range"Go
• Deleted redundant PLL specification in the Recommended Operating Conditions Go
• Deleted "Intelligent clock error..." and "...for pop-free performance."Go
• Clarified clock generation explanationGo
• Clarified external SCK discussion.Go
• Deleted "The PCM510xA disables the internal PLL when an external SCK is supplied."Go

Changes from * Revision (May 2012) to A Revision

• Changed 前兩頁(yè)的編排Go
• Changed "VOUT = –1 dB" to "THD+N at –1 dBFS" in in the Dymamic Performance section of the Electrical CharacteristicsGo
• Changed reference to correct footnoteGo
• Changed t_SCKH and t_SCKL values to 9ns.Go
• Removed 48kHz sample rate with PLL-generated clockGo