ZHCSMZ3A December 2020 – June 2021 PCM1820 , PCM1821
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Hardware Control
- 8.3.2 Audio Serial Interfaces
- 8.3.3 Phase-Locked Loop (PLL) and Clock Generation
- 8.3.4 Input Channel Configurations
- 8.3.5 Reference Voltage
- 8.3.6
Signal-Chain Processing
- 8.3.6.1 Digital High-Pass Filter
- 8.3.6.2
Configurable Digital Decimation Filters
- 8.3.6.2.1
Linear Phase Filters
- 8.3.6.2.1.1 Sampling Rate: 8 kHz or 7.35 kHz
- 8.3.6.2.1.2 Sampling Rate: 16 kHz or 14.7 kHz
- 8.3.6.2.1.3 Sampling Rate: 24 kHz or 22.05 kHz
- 8.3.6.2.1.4 Sampling Rate: 32 kHz or 29.4 kHz
- 8.3.6.2.1.5 Sampling Rate: 48 kHz or 44.1 kHz
- 8.3.6.2.1.6 Sampling Rate: 96 kHz or 88.2 kHz
- 8.3.6.2.1.7 Sampling Rate: 192 kHz or 176.4 kHz
- 8.3.6.2.2 Low-Latency Filters
- 8.3.6.2.1
Linear Phase Filters
- 8.3.7 Dynamic Range Enhancer (DRE)
- 8.4 Device Functional Modes
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- RTE|20
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
訂購信息
8.3.2.1 Time Division Multiplexed Audio (TDM) Interface
In TDM mode, also known as DSP mode, the rising edge of FSYNC starts the data transfer with the slot 0 data first. Immediately after the slot 0 data transmission, the remaining slot data are transmitted in order. FSYNC and each data bit (except the MSB of slot 0 when TX_OFFSET equals 0) is transmitted on the rising edge of BCLK. Figure 8-1 and Figure 8-2 show the protocol timing for TDM operation with various configurations.
Figure 8-1 TDM Mode
Protocol Timing (FMT0 = HIGH) In Slave Mode
Figure 8-2 TDM Mode
Protocol Timing (FMT0 = HIGH) In Master ModeFor proper operation of the audio bus in TDM mode, the number of bit clocks per frame must be greater than or equal to the number of active output channels times the 32-bits word length of the output channel data. The device transmits a zero data value on SDOUT for the extra unused bit clock cycles. The device supports FSYNC as a pulse with a 1-cycle-wide bit clock, but also supports multiples as well.