ZHCSK28E April 2003 – July 2019 PCM1753 , PCM1754 , PCM1755
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 修訂歷史記錄
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3 Feature Description
- 8.4 Device Functional Modes
- 8.5 Programming
- 8.6
Register Maps
- 8.6.1
Mode Control Registers (PCM1753/55)
- 8.6.1.1 User-Programmable Mode Controls
- 8.6.1.2
Register Definitions
- 8.6.1.2.1 ATx[7:0]: Digital Attenuation Level Setting
- 8.6.1.2.2 MUTx: Soft Mute Control
- 8.6.1.2.3 OVER: Oversampling Rate Control
- 8.6.1.2.4 SRST: Reset
- 8.6.1.2.5 DACx: DAC Operation Control
- 8.6.1.2.6 DM12: Digital De-Emphasis Function Control
- 8.6.1.2.7 DMF[1:0]: Sampling Frequency Selection for the De-Emphasis Function
- 8.6.1.2.8 FMT[2:0]: Audio Interface Data Format
- 8.6.1.2.9 FLT: Digital Filter Rolloff Control
- 8.6.1.2.10 DREV: Output Phase Select
- 8.6.1.2.11 ZREV: Zero Flag Polarity Select
- 8.6.1.2.12 AZRO: Zero Flag Function Select
- 8.6.1
Mode Control Registers (PCM1753/55)
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機(jī)械、封裝和可訂購信息
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- DBQ|16
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
訂購信息
7.8 Control Interface Timing Requirements
these timing parameters are critical for proper control port operation| MIN | NOM | MAX | UNIT | |||
|---|---|---|---|---|---|---|
| t(MCY) | MC pulse cycle time | See Figure 1. | 100 | ns | ||
| t(MCL) | MC low-level time | 50 | ns | |||
| t(MCH) | MC high-level time | 50 | ns | |||
| t(MCH) | ML high-level time | See (1) | ns | |||
| t(MLS) | ML falling edge to MC rising edge | 20 | ns | |||
| t(MLH) | ML hold time(2) | 20 | ns | |||
| t(MDH) | MD hold time | 15 | ns | |||
| t(MCS) | MD setup time | 20 | ns | |||
(1) 
seconds (min); fS: sampling rate.
seconds (min); fS: sampling rate.(2) MC rising edge for LSB to ML rising edge.
Figure 1. Control Interface Timing