8.3.1.1 Equalizer

The data signal is applied to an input equalizer by means of the input signal pins TXIN+ / TXIN–, which provide on-chip differential 100-Ω line termination. The equalizer is enabled by default and can be disabled by setting the transmitter equalizer disable bit TXEQ_DIS = 1 (bit 1 of register 10). Equalization of up to 300 mm (12 inches) of microstrip or stripline transmission line on FR4 printed circuit boards can be achieved. The amount of equalization is set through register settings TXCTLE [0..3] (register 11). The device can accept input amplitude levels from 100 mVpp up to 1000 mVpp.

8.3.1.2 CDR

The clock and data recovery function consists of a Phase-Locked Loop (PLL) and retimer. The CDR can be operated without a reference clock and the Voltage Controlled Oscillator (VCO) can cover 9.8 Gbps to 11.7 Gbps data rates. The PLL is phase locked to the incoming data stream and attenuates the high frequency jitter on the data, producing a recovered clean clock with substantially reduced jitter. An external capacitor for the PLL loop filter is connected to the TX_LF pin. A value of 2.2 nF is recommended. The clean clock is used to retime the incoming data, producing an output signal with reduced jitter, and in effect, resetting the jitter budget for the transmitter.

The CDR is enabled by default. The CDR can be disabled and bypassed by setting the transmitter CDR disable bit TXCDR_DIS = 1 (bit 4 of register 10). Alternatively, the CDR can be left powered on but bypassed by setting the transmitter CDR bypass bit TX_CDRBP = 1 (bit 3 of register 10); however, this function only works if the receiver CDR bypass bit RX_CDRBP (bit 3 of register 4) is also set to 1.

The CDR is designed to meet the XFP Datacom requirements and Telecom requirements for a maximum of 1-dB jitter peaking at a frequency greater than 120 kHz. The CDR is not designed to meet the Telecom regenerator requirements of jitter peaking less than 0.03 dB at a frequency less than 120 kHz. The default CDR bandwidth is typically 4.5 MHz and can be adjusted using the SEL_RES[0..2] bits (bits 5 to 7 of register 51). Adjusting these bits changes the bandwidth of both the transmitter and receiver CDRs.

For the majority of applications, the default settings in register 19 for the transmitter CDR can be used. However, for some applications or for test purposes, some modes of operation may be useful. The frequency detector for the PLL is set to an automatic mode of operation by default. When a signal is applied to the transmitter input the frequency detector search algorithm will be initiated to determine the frequency of the data. The default algorithm ensures a fast CDR lock time of less than 2 ms. The fast lock can be disabled by setting the transmitter CDR fast lock disable bit TXFL_DIS = 1 (bit 3 of register 19). Once the frequency has been detected then the frequency detector will be disabled and the supply current will decrease by approximately 10mA. In some applications, such as when there are long periods of idle data, it may be advantageous to keep the frequency detector permanently enabled by setting the transmitter frequency detector enable bit TXFD_EN = 1 (bit 5 of register 19). For test purposes, the frequency detector can be permanently disabled by setting the transmitter frequency detector disable bit TXFD_DIS = 1 (bit 4 of register 19). For fast lock times the frequency detector can be set to one of two preselected data rates using the transmitter frequency detection mode selection bits TXFD_MOD[0..1] (bits 6 and 7 of register 19). If it is desired to use the retimer at lower data rates than the standard 9.8 to 11.7Gbps then the transmitter divider ratio should be adjusted accordingly through TXDIV[0..2] (bits 0 to 2 of register 19). For example, for re-timed operation at 2.5 Gbps the divider should be set to divide by 4.

8.3.1.3 Modulator Driver

The modulation current is sunk from the common emitter node of the limiting output driver differential pair by means of a modulation current generator, which is digitally controlled by the 2-wire serial interface.

The collector nodes of the output stages are connected to the transmitter output pins TXOUT+ and TXOUT–. The collectors have internal 50Ω back termination resistors to VCC_TX. The outputs are optimized to drive a 50 Ω single-ended load and to obtain the maximum single-ended output voltage of 2.0Vpp, AC coupling and inductive pull-ups to VCC are required. For reduced power consumption the DC resistance of the inductive pull-ups should be minimized to provide sufficient headroom on the TXOUT+ and TXOUT– pins.

The polarity of the output pins can be inverted by setting the transmitter output polarity switch bit, TXOUTPOL (bit 5 of register 10) to 1. In addition, the output driver can be disabled by setting the transmitter output driver disable bit TXOUT_DIS = 1 (bit 6 of register 10).

The output driver is set to differential output by default. In order to reduce the power consumption for single-ended applications driving an electroabsorptive modulated laser (EML) the output drive register 13 should be set to single-ended mode. The single-ended output signal is enabled by setting the transmitter mode select bit TXMODE = 1 (bit 6 of register 13). The positive output is active by default. To enable the negative output and disable the positive output set TXOUTSEL = 1 (bit 7 of register 13).

Output de-emphasis can be applied to the signal by adjusting the transmitter de-emphasis bits TXDEADJ[0..3] (bits 0 to 3 of register 13). In addition, the width of the applied de-emphasis can be increased by setting the transmitter output peaking width TXPKSEL = 1 (bit 6 of register 11). The wide peaking width would typically be useful for a more capacitive transmitter load. How de-emphasis is applied is controlled through the TXSTEP bit (bit 5 of register 13). Setting TXSTEP = 1 delays the time of the applied de-emphasis and has more of an impact on the falling edge. A graphical representation of the two de-emphasis modes is shown in Figure 37. Using de-emphasis can help to optimize the transmitted output signal; however, it will add to the power consumption.

The output edge speed can be set to slow mode of operation through the TXSLOW bit (bit 4 of register 13). For transmitter modulation output settings (TXMOD - register 12) below 0xC0 it is recommended to set TXSLOW = 1 to reduce the output jitter.

Figure 37. Transmitter De-Emphasis Modes

8.3.1.4 Modulation Current Generator

The modulation current generator provides the current for the high speed output driver described above. The circuit can be digitally controlled through the 2-wire interface block or controlled by applying an analog voltage in the range of 0 to 2V to the AMP pin. The default method of control is through the 2-wire interface. To use the AMP pin set the transmitter amplitude control bit TXAMPCTRL = 1 (bit 0 of register 10).

An 8-bit wide control bus, TXMOD[0..7] (register 12), is used to set the desired modulation current and the output voltage.

The entire transmitter signal path, including CDR, can be disabled and powered down by setting TX_DIS = 1 (bit 7 of register 10).

8.3.1.5 DC Offset Cancellation and Cross Point Control

The ONET1130EC transmitter has DC offset cancellation to compensate for internal offset voltages. The offset cancellation can be disabled by setting TXOC_DIS = 1 (bit 2 of register 10).

The crossing point can be moved toward the one level by setting TXCPSGN = 1 (bit 7 of register 14) and it can be moved toward the zero level by setting TXCPSGN = 0. The percentage of shift depends upon the register settings of the transmitter cross-point adjustment bits TXCPADJ[0..6] (register 14).

8.3.1.6 Transmitter Loopback (Electrical Loopback)

The signal input to the TXIN+ and TXIN– pins can be looped back to the receiver output after the retimer as shown in Figure 38 by setting TX_LBMUX = 1 (bit 0 of register 2). Loopback from the receiver input to the transmitter output (optical loopback) can be enabled at the same time.

If it is desired to loopback the signal input to the TXIN+ and TXIN– pins to the receiver output with the CDR disabled then the transmit CDR must be disabled and bypassed by setting TXCDR_DIS = 1 (bit 4 of register 10) and the receiver CDR must also be disabled and bypassed by setting RXCDR_DIS =1 (bit 4 of register 4).

Figure 38. Electrical Loopback

8.3.1.7 Bias Current Generation and APC Loop

The bias current for the laser is turned off by default and has to be enabled by setting the laser bias current enable bit TXBIASEN = 1 (bit 2 of register 1). In open loop operation, selected by setting TXOLENA = 1 (bit 4 of register 1), the bias current is set directly by the 10-bit wide control word TXBIAS[0..9] (register 15 and register 16). In Automatic Power Control (APC) mode, selected by setting TXOLENA = 0, the bias current depends on the register settings TXBIAS[0..9] and the coupling ratio (CR) between the laser bias current and the photodiode current. CR = I_BIAS/I_PD. If the photodiode cathode is connected to VCC and the anode is connected to the PD pin (PD pin is sinking current) set TXPDPOL = 1 (bit 0 of register 1). If the photodiode anode is connected to ground and the cathode is connected to the PD pin (PD pin is sourcing current), set TXPDPOL = 0.

Three photodiode current ranges can be selected by means of the photodiode current range bits TXPDRNG[0..1] (bits 5 and 6 of register 1). The photodiode range should be chosen to keep the laser bias control DAC, TXBIAS[0..9], close to the center of its range. This keeps the laser bias current set point resolution high. For details regarding the bias current setting in open-loop mode as well as in closed-loop mode, see the Register Mapping table.

The ONET1130EC has the ability to source or sink the bias current. The default condition is for the BIAS pin to source the current (TXBIASPOL = 0). To act as a sink, set TXBIASPOL = 1 (bit 1 of register 1).

The bias current is monitored using a current mirror with a gain equal to 1/100. By connecting a resistor between MONB and GND, the bias current can be monitored as a voltage across the resistor. A low temperature coefficient precision resistor should be used. The bias current can also be monitored as a 10 bit unsigned digital word by setting the transmitter bias current digital monitor selection bit TXDMONB = 1 (bit 5 of register 16) and removing the resistor from MONB to ground.

The photodiode current is monitored using a current mirror with various gains that are dependent upon the photodiode current range being used. By connecting a resistor between MONP and GND, the photodiode current can be monitored as a voltage across the resistor. A low temperature coefficient precision resistor should be used. The photodiode current can also be monitored as a 10 bit unsigned digital word by setting the transmitter photodiode current digital monitor selection bit TXDMONP = 1 (bit 6 of register 16) and removing the resistor from MONP to ground.

8.3.1.8 Laser Safety Features and Fault Recovery Procedure

The ONET1130EC provides built in laser safety features. The following fault conditions are detected if the transmitter fault detection enable bit TXFLTEN = 1 (bit 3 of register 1):

1. Voltage at MONB exceeds the bandgap voltage (1.2 V) or, alternately, if TXDMONB = 1 and the bias current exceeds the bias current monitor fault threshold set by TXBMF[0..7] (register 17). When using the digital monitor, the resistor from the MONB pin to ground must be removed.
2. Voltage at MONP exceeds the bandgap voltage (1.2 V) and the analog photodiode current monitor fault trigger bit, TXMONPFLT (bit 7 of register 1), is set to 1. Alternately, a fault can be triggered if TXDMONP = 1 and the photodiode current exceeds the photodiode current monitor fault threshold set by TXPMF[0..7] (register 18). When using the digital monitor, the resistor from the MONP pin to ground must be removed.
3. Photodiode current exceeds 150% of its set value,
4. Bias control DAC drops in value by more than 50% in one step.

If the fault detection is being used then to avoid a fault from occurring at start-up it is recommended to set up the required bias current and APC loop conditions first and enable the laser bias current (TXBIASEN = 1) as the last step in the sequence of commands.

If one or more fault conditions occur and the transmitter fault enable bit TXFLTEN is set to 1, the ONET1130EC responds by:

1. Setting the bias current to zero.
2. Asserting and latching the TX_FLT pin.
3. Setting the TX_FLT bit (bit 5 of register 43) to 1.

Fault recovery is performed by the following procedure:

1. The transmitter disable pin TX_DIS and/or the transmitter bias current enable bit TXBIASEN are toggled for at least the fault latch reset time.
2. The TX_FLT pin de-asserts while the transmitter disable pin TX_DIS is asserted or the transmitter bias current enable bit TXBIASEN is de-asserted.
3. If the fault condition is no longer present, the part will return to normal operation with its prior output settings after the disable negate time.
4. If the fault condition is still present, TX_FLT re-asserts once TX_DIS is set to a low level and/or TXBIASEN is set to 0 and the part will not return to normal operation.

8.3.2.1 Equalizer

The data signal is applied to an input equalizer by means of the input signal pins RXIN+ / RXIN–, which provide on-chip differential 100 Ω line-termination. The equalizer is enabled by default and can be disabled by setting the receiver equalizer disable bit RXEQ_DIS = 1 (bit 1 of register 4). Equalization is provided for bandwidth compensation of the optical receiver. The amount of equalization is set through the register settings RXCTLE [0..2] (register 5). The device can accept input amplitude levels from 6 mVpp up to 800 mVpp.

8.3.2.2 DC Offset Cancellation and Cross Point Control

Receiver offset cancellation compensates for internal offset voltages and thus ensures proper operation even for very small input data signals. The offset cancellation is enabled by default and the input threshold voltage can be adjusted using register settings RXTHADJ[0..3] (register 6) to optimize the bit error rate or change the eye crossing point to compensate for input signal pulse width distortion. The offset cancellation can be disabled by setting RXOC_DIS = 1 (bit 2 of register 4) and this also disables the cross point adjustment.

8.3.2.3 CDR

The receiver clock and data recovery function consists of a Phase-Locked Loop (PLL) and retimer. The CDR can be operated without a reference clock and the Voltage Controlled Oscillator (VCO) can cover 9.8Gbps to 11.7 Gbps data rates. The PLL is phase locked to the incoming data stream and attenuates the high frequency jitter on the data, producing a recovered clean clock with substantially reduced jitter. An external capacitor for the PLL loop filter is connected to the RX_LF pin. A value of 2.2 nF is recommended. The clean clock is used to retime the incoming data, producing an output signal with reduced jitter, and in effect, resetting the jitter budget for the receiver.

The CDR is enabled by default. The CDR can be disabled and bypassed by setting the receiver CDR disable bit RXCDR_DIS = 1 (bit 4 of register 4). Alternatively, the CDR can be left powered on but bypassed by setting the receiver CDR bypass bit RX_CDRBP = 1 (bit 3 of register 4); however, this only works if the transmitter CDR bypass bit TX_CDRBP (bit 3 of register 10) is also set to 1.

The CDR is designed to meet the XFP Datacom requirements and Telecom requirements for a maximum of 1 dB jitter peaking at a frequency greater than 120 kHz. The CDR is not designed to meet the Telecom regenerator requirements of jitter peaking less than 0.03 dB at a frequency less than 120 kHz.The default CDR bandwidth is typically 4.5 MHz and can be adjusted using the SEL_RES[0..2] bits (bits 5 to 7 of register 51). Adjusting these bits changes the bandwidth of both the receiver and transmitter CDRs.

For the majority of applications the default settings in register 9 for the receiver CDR can be used. However, for some applications or for test purposes, some modes of operation may be useful. The frequency detector for the PLL is set to an automatic mode of operation by default. When a signal is applied to the receiver input the frequency detector search algorithm will be initiated to determine the frequency of the data. The default algorithm ensures a fast CDR lock time of less than 2 ms. The fast lock can be disabled by setting the receiver CDR fast lock disable bit RXFL_DIS = 1 (bit 3 of register 9). Once the frequency has been detected then the frequency detector will be disabled and the supply current will decrease by approximately 10 mA. In some applications, such as when there are long periods of idle data, it may be advantageous to keep the frequency detector permanently enabled by setting the receiver frequency detector enable bit RXFD_EN = 1 (bit 5 of register 9). For test purposes, the frequency detector can be permanently disabled by setting the receiver frequency detector disable bit RXFD_DIS = 1 (bit 4 of register 9). For fast lock times the frequency detector can be set to one of two preselected data rates using the receiver frequency detection mode selection bits RXFD_MOD[0..1] (bits 6 and 7 of register 9). If it is desired to use the retimer at lower data rates than the standard 9.8 to 11.7 Gbps then the receiver divider ratio should be adjusted accordingly through RXDIV[0..2] (bits 0 to 2 of register 9). For example, for retimed operation at 2.5 Gbps the divider should be set to divide by 4.

8.3.2.4 Output Driver

The output amplitude of the driver can be varied from 300 mVpp to 900 mVpp using the register settings RXAMP[0..3] (register 8). The default amplitude setting is 300 mVpp. To compensate for frequency dependent losses of transmission lines connected to the output, adjustable de-emphasis is provided. The de-emphasis can be adjusted using RXDADJ[0..2] (register 8). The polarity of the output pins can be inverted by setting the receiver output polarity switch bit RXOUTPOL = 1 (bit 5 of register 4).

In addition, the output driver can be disabled by setting the receiver output driver disable bit RXOUT_DIS = 1 (bit 6 of register 4) or the receiver signal path can be disabled and powered down by setting RX_DIS = 1 (bit 7 of register 4).

8.3.2.5 Receiver Loopback (Optical Loopback)

The signal input to the RXIN+ and RXIN– pins can be looped back to the transmitter output after the retimer as shown in Figure 39 by setting RX_LBMUX = 1 (bit 1 of register 2). Loopback from the transmitter input to the receiver output (electrical loopback) can be enabled at the same time.

If it is desired to loopback the signal input to the RXIN+ and RXIN– pins to the transmitter output with the CDR disabled then the receive CDR must be disabled and bypassed by setting RXCDR_DIS = 1 (bit 4 of register 4) and the transmit CDR must also be disabled and bypassed by setting TXCDR_DIS =1 (bit 4 of register 10).

Figure 39. Optical Loopback

8.3.2.6 Loss of Signal Detection

The loss of signal (LOS) detection is done by 2 separate level detectors to cover a wide dynamic range. The peak values of the input signal are monitored by a peak detector and compared to a pre-defined loss of signal threshold voltage inside the loss of signal detection block. As a result of the comparison, the LOS signal, which indicates that the input signal amplitude is below the defined threshold level, is generated. There are 2 LOS ranges settable with the RXLOSRNG bit (bit 0 of register 4). With RXLOSRNG = 0 the high range of the LOS assert values are used (40 mV_PP to 130 mV_PP) and by setting RXLOSRNG = 1 the low range of the LOS assert values are used (10 mV_PP to 50 mV_PP). There are 64 possible internal LOS settings set with RXLOSA[0..5] (register 7) for each LOS range to adjust the LOS assert level.

The typical LOS hysteresis, as defined by 20log(LOS de-assert voltage/LOS assert voltage) is 4 dB. This can be reduced by approximately 2 dB by setting receiver hysteresis RXHYS = 1 (bit 7 of register 6). In addition, the LOS detection time can be reduced by setting the receiver fast LOS bit RXFLOS = 1 (bit 3 of register 5); however, this may result in chatter (LOS bounce).

8.3.3.1 Analog Reference and Temperature Sensor

The ONET1130EC is supplied by a single 2.5 V ±5% supply voltage connected to the VCC_TX, VCC_RX and VDD pins. This voltage is referred to ground (GND) and can be monitored as a 10 bit unsigned digital word through the 2-wire interface.

On-chip bandgap voltage circuitry generates a reference voltage, independent of the supply voltage, from which all other internally required voltages and bias currents are derived.

In order to minimize the module component count, the ONET1130ECprovides an on-chip temperature sensor. The temperature can be monitored as a 10 bit unsigned digital word through the 2-wire interface.

8.3.3.2 Power-On Reset

The ONET1130EC has power on reset circuitry which ensures that all registers are reset to default values during startup. After the power-on to initialize time (t_INIT1), the internal registers are ready to be loaded. The part is ready to transmit data after the initialize to transmit time (t_INIT2), assuming that the enable chip bit EN_CHIP = 1 (bit 0 of register 0). In addition, the transmitter disable pin TX_DIS and receiver disable pin RX_DIS must be set to zero.

The ONET1130EC bias current can be disabled by setting the TX_DIS pin high. The internal registers are not reset. After the transmitter disable pin TX_DIS is set low the part returns to its prior output settings.

8.3.3.3 Analog to Digital Converter

The ONET1130EC has an internal 10 bit analog to digital converter (ADC) that converts the analog monitors for temperature, power supply voltage, bias current and photodiode current into a 10 bit unsigned digital word. The first 8 most significant bits (MSBs) are available in register 40 and the 2 least significant bits (LSBs) are available in register 41. Depending on the accuracy required, 8 bits or 10 bits can be read. However, due to the architecture of the 2-wire interface, in order to read the 2 registers, 2 separate read commands have to be sent.

The ADC is enabled by default so to monitor a particular parameter, select the parameter with ADCSEL[0..2] (bits 0 to 2 of register 3). Table 2 shows the ADCSEL bits and the parameter that is monitored.

To digitally monitor the photodiode current, ensure that TXDMONP = 1 (bit 6 of register 16) and that a resistor is not connected to the MONP pin. To digitally monitor the bias current, ensure that TXDMONB = 1 (bit 5 of register 16) and that a resistor is not connected to the MONB pin. The ADC is disabled by default. To enable the ADC, set the ADC oscillator enable bit OSCEN = 1 (bit 6 of register 3) and set the ADC enable bit ADCEN = 1 (bit 7 of register 3).

The digital word read from the ADC can be converted to its analog equivalent through the following formulas.

Where: ADCx = the decimal value read from the ADC

8.3.3.4 2-Wire Interface and Control Logic

The ONET1130EC uses a 2-wire serial interface for digital control. The two circuit inputs, SDA and SCK, are driven, respectively, by the serial data and serial clock from a microprocessor, for example. The SDA and SCK pins require external 4.7-kΩ to 10-kΩ pull-up resistor to VCC for proper operation.

The 2-wire interface allows write access to the internal memory map to modify control registers and read access to read out the control signals. The ONET1130EC is a slave device only which means that it cannot initiate a transmission itself; it always relies on the availability of the SCK signal for the duration of the transmission. The master device provides the clock signal as well as the START and STOP commands. The protocol for a data transmission is as follows:

1. START command
2. Seven (7) bit slave address (0001000) followed by an eighth bit which is the data direction bit (R/W). A zero indicates a WRITE and a 1 indicates a READ.
3. 8 bit register address
4. 8 bit register data word
5. STOP command

Regarding timing, the ONET1130EC is I²C compatible. The typical timing is shown in Figure 2 and a complete data transfer is shown in Figure 40. Parameters for Figure 2 are defined in Table 1.

8.3.3.5 Bus Idle

Both SDA and SCK lines remain HIGH

8.3.3.6 Start Data Transfer

A change in the state of the SDA line, from HIGH to LOW, while the SCK line is HIGH, defines a START condition (S). Each data transfer is initiated with a START condition.

8.3.3.7 Stop Data Transfer

A change in the state of the SDA line from LOW to HIGH while the SCK line is HIGH defines a STOP condition (P). Each data transfer is terminated with a STOP condition; however, if the master still wishes to communicate on the bus, it can generate a repeated START condition and address another slave without first generating a STOP condition.

8.3.3.8 Data Transfer

Only one data byte can be transferred between a START and a STOP condition. The receiver acknowledges the transfer of data.

8.6.1.1 Core Level Register 0 (offset = 0100 0001 [reset = 41h]

8.6.1.2 Core Level Register 1 (offset = 0000 0000) [reset = 0h]

8.6.1.3 Core Level Register 2 (offset = 0000 0000 ) [reset = 0h]

8.6.1.4 Core Level Register 3 (offset = 0000 0000) [reset = 0h]

8.6.2.1 RX Register 4 (offset = 0000 0000) [reset = 0h]

8.6.2.2 RX Register 5 (offset = 0000 0000) [reset = 0h]

8.6.2.3 RX Register 6 (offset = 0000 0000) [reset = 0h]

8.6.2.4 RX Register 7 (offset = 0000 0000) [reset = 0h]

8.6.2.5 RX Register 8 (offset = 0000 0000) [reset = 0h]

8.6.2.6 RX Register 9 (offset = 0000 0000) [reset = 0h]

8.6.3.1 TX Register 10 (offset = 0000 0000) [reset = 0h]

8.6.3.2 TX Register 11 (offset = 0000 0000) [reset = 0h]

8.6.3.3 TX Register 12 (offset = 0000 0000) [reset = 0h]

8.6.3.4 TX Register 13 (offset = 0h) [reset = 0]

8.6.3.5 TX Register 14 (offset = 0000 0000) [reset = 0h]

8.6.3.6 TX Register 15 (offset = 0000 0000) [reset = 0h]

8.6.3.7 TX Register 16 (offset = 0000 0000) [reset = 0h]

8.6.3.8 TX Register 17 (offset = 0000 0000) [reset = 0h]

8.6.3.9 TX Register 18 (offset = 0000 0000) [reset = 0h]

8.6.3.10 TX Register 19 (offset = 0000 0000) [reset = 0h]

8.6.4.1 Reserved Registers 20-39

8.6.5.1 Core Level Register 40 (offset = 0000 0000) [reset = 0h]

8.6.5.2 Core Level Register 41 (offset = 0000 0000) [reset = 0h]

8.6.5.3 RX Registers 42 (offset = 0000 0000) [reset = 0h]

8.6.5.4 TX Register 43 (offset = 0000 0000) [reset = 0h]

8.6.6.1 Adjustment Registers 44-50

8.6.6.2 Adjustment Register 51 (offset = 0100 0000) [reset = 40h]