ZHCSD73D August 2012 – August 2018 LMZ21700
PRODUCTION DATA.
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
Figure 1. LMZ21700 in the SIL0008E Package
| PIN | I/O | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| SS | 1 | I | Soft-start pin. An external capacitor connected to this pin sets the internal voltage reference ramp time. It can be used for tracking and sequencing. |
| FB | 2 | I | Voltage feedback. Connect resistive voltage divider to this pin to set the output voltage. |
| PG | 3 | O | Output power good (High = VOUT ready, Low = VOUT below nominal regulation); open drain (requires pull-up resistor; goes low impedance when EN is low) |
| VOUT | 4 | O | Output Voltage. Connected to one terminal of the integrated inductor. Connect output filter capacitor between VOUT and PGND. |
| GND | 5 | I | Ground for the power MOSFETs and gate-drive circuitry. |
| VOS | 6 | I | Output voltage sense pin and connection for the control loop circuitry. |
| EN | 7 | I | Enable input (High = enabled, Low = disabled). Internal pull down resistor keeps logic level low if pin is left floating |
| VIN | 8 | I | Supply voltage for control circuitry and power stage. |
| PAD | Electrically connected to GND. Must be soldered to a ground copper plane to achieve appropriate power dissipation and mechanical reliability. | ||