ZHCSO17C November 2019 – March 2022 LMX2694-SEP
PRODUCTION DATA
The LMX2694-SEP can generate a SYSREF output signal that is synchronized to fOUT with a programmable delay. This output can be a single pulse, series of pulses, or a continuous stream of pulses. To use the SYSREF capability, the PLL must first be placed in SYNC mode with VCO_PHASE_SYNC = 1.
Figure 7-6 SYSREF SetupAs Figure 7-6 shows, the SYSREF feature uses IncludedDivide and SYSREF_DIV_PRE divider to generate fINTERPOLATOR. This frequency is used for re-clocking of the rising and falling edges at the SYSREFREQ pin. In master mode, the fINTERPOLATOR is further divided by 2 × SYSREF_DIV to generate finite series or continuous stream of pulses.
| PARAMETER | MIN | TYP | MAX | UNIT |
|---|---|---|---|---|
| fVCO | 7550 | 15100 | MHz | |
| fINTERPOLATOR | 0.8 | 1.5 | GHz | |
| IncludedDivide | 4 or 6 | |||
| SYSREF_DIV_PRE | 1, 2, or 4 | |||
| SYSREF_DIV | 4, 6, 8, ..., 4098 | |||
| fINTERPOLATOR | fINTERPOLATOR = fVCO / (IncludedDivide × SYSREF_DIV_PRE) | |||
| fSYSREF | fSYSREF = fINTERPOLATOR / (2 × SYSREF_DIV) | |||
| Delay step size | 9 | ps | ||
| Pulses for pulsed mode (SYSREF_PULSE_CNT) | 0 | 15 | ||
The delay can be programmed using the JESD_DAC1_CTRL, JESD_DAC2_CTRL, JESD_DAC3_CTRL, and JESD_DAC4_CTRL words. By concatenating these words into a larger word called "SYSREFPHASESHIFT", the relative delay can be found. The sum of these words must always be 63.
| SYSREFPHASESHIFT | DELAY | JESD_DAC1 | JESD_DAC2 | JESD_DAC3 | JESD_DAC4 |
|---|---|---|---|---|---|
| 0 | Minimum | 36 | 27 | 0 | 0 |
| ... | 0 | 0 | |||
| 36 | 0 | 63 | 0 | 0 | |
| 37 | 0 | 62 | 1 | 0 | |
| ... | |||||
| 99 | 0 | 0 | 63 | 0 | |
| 100 | 0 | 0 | 62 | 1 | |
| ... | |||||
| 161 | 0 | 0 | 1 | 62 | |
| 162 | 0 | 0 | 0 | 63 | |
| 163 | 1 | 0 | 0 | 62 | |
| 225 | 63 | 0 | 0 | 0 | |
| 226 | 62 | 1 | 0 | 0 | |
| 247 | Maximum | 41 | 22 | 0 | 0 |
| > 247 | Invalid | Invalid | Invalid | Invalid | Invalid |