ZHCSIC4C June 2018 – November 2018 LMX2615-SP
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說(shuō)明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Reference Oscillator Input
- 7.3.2 Reference Path
- 7.3.3 State Machine Clock
- 7.3.4 PLL Phase Detector and Charge Pump
- 7.3.5 N Divider and Fractional Circuitry
- 7.3.6 MUXout Pin
- 7.3.7 VCO (Voltage Controlled Oscillator)
- 7.3.8 Channel Divider
- 7.3.9 Output Buffer
- 7.3.10 Powerdown Modes
- 7.3.11 Treatment of Unused Pins
- 7.3.12 Phase Synchronization
- 7.3.13 Phase Adjust
- 7.3.14 Fine Adjustments for Phase Adjust and Phase SYNC
- 7.3.15 SYSREF
- 7.3.16 Pin Modes
- 7.4 Device Functional Modes
- 7.5 Programming
- 7.6
Register Maps
- 7.6.1
Register Map
- 7.6.1.1 R0 Register (Address = 0x0) [reset = X]
- 7.6.1.2 R1 Register (Address = 0x1) [reset = 0x4]
- 7.6.1.3 R8 Register (Address = 0x8) [reset = X]
- 7.6.1.4 R9 Register (Address = 0x9) [reset = X]
- 7.6.1.5 R11 Register (Address = 0xB) [reset = 0x10]
- 7.6.1.6 R12 Register (Address = 0xC) [reset = 0x1]
- 7.6.1.7 R14 Register (Address = 0xE) [reset = 0x70]
- 7.6.1.8 R16 Register (Address = 0x10) [reset = 0x80]
- 7.6.1.9 R19 Register (Address = 0x13) [reset = 0xB7]
- 7.6.1.10 R20 Register (Address = 0x14) [reset = X]
- 7.6.1.11 R31 Register (Address = 0x1F) [reset = X]
- 7.6.1.12 R34 Register (Address = 0x22) [reset = 0x0]
- 7.6.1.13 R36 Register (Address = 0x24) [reset = 0x46]
- 7.6.1.14 R37 Register (Address = 0x25) [reset = 0x400]
- 7.6.1.15 R38 Register (Address = 0x26) [reset = 0xFD51]
- 7.6.1.16 R39 Register (Address = 0x27) [reset = 0xDA80]
- 7.6.1.17 R40 Register (Address = 0x28) [reset = 0x0]
- 7.6.1.18 R41 Register (Address = 0x29) [reset = 0x0]
- 7.6.1.19 R42 Register (Address = 0x2A) [reset = 0x0]
- 7.6.1.20 R43 Register (Address = 0x2B) [reset = 0x0]
- 7.6.1.21 R44 Register (Address = 0x2C) [reset = 0x1FA3]
- 7.6.1.22 R45 Register (Address = 0x2D) [reset = X]
- 7.6.1.23 R46 Register (Address = 0x2E) [reset = 0x1]
- 7.6.1.24 R58 Register (Address = 0x3A) [reset = X]
- 7.6.1.25 R59 Register (Address = 0x3B) [reset = 0x1]
- 7.6.1.26 R60 Register (Address = 0x3C) [reset = 0x9C4]
- 7.6.1.27 R69 Register (Address = 0x45) [reset = 0x0]
- 7.6.1.28 R70 Register (Address = 0x46) [reset = 0xC350]
- 7.6.1.29 R71 Register (Address = 0x47) [reset = 0x80]
- 7.6.1.30 R72 Register (Address = 0x48) [reset = 0x1]
- 7.6.1.31 R73 Register (Address = 0x49) [reset = 0x3F]
- 7.6.1.32 R74 Register (Address = 0x4A) [reset = 0x0]
- 7.6.1.33 R75 Register (Address = 0x4B) [reset = 0x0]
- 7.6.1.34 R110 Register (Address = 0x6E) [reset = 0x0]
- 7.6.1.35 R111 Register (Address = 0x6F) [reset = 0x0]
- 7.6.1.36 R112 Register (Address = 0x70) [reset = 0x0]
- 7.6.1.37 R113 Register (Address = 0x71) [reset = 0x0]
- 7.6.1.38 R114 Register (Address = 0x72) [reset = 0x26F]
- 7.6.1
Register Map
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機(jī)械、封裝和可訂購(gòu)信息
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- HBD|64
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
訂購(gòu)信息
6.6 Timing Requirements
(3.2 V ≤ VCC ≤ 3.45 V, –55°C ≤ TA ≤+125°C, except as specified. Nominal values are at VCC = 3.3 V,TA = 25°C)| MIN | NOM | MAX | UNIT | |||
|---|---|---|---|---|---|---|
| DIGITAL INTERFACE WRITE SPECIFICATIONS | ||||||
| fSPIWrite | SPI write speed | 2 | MHz | |||
| tCE | Clock to enable low time | See Figure 1 | 50 | ns | ||
| tCS | Data to clock setup time | 50 | ns | |||
| tCH | Data to clock hold time | 50 | ns | |||
| tCWH | Clock pulse width high | 200 | ns | |||
| tCWL | Clock pulse width low | 200 | ns | |||
| tCES | Enable to clock setup time | 100 | ns | |||
| tEWH | Enable pulse width high | 100 | ns | |||
| DIGITAL INTERFACE READBACK SPECIFICATIONS | ||||||
| fSPIReadback | SPI readback speed | See Figure 2 | 2 | MHz | ||
| tCE | Clock to enable low time | See Figure 2 | 50 | ns | ||
| tCS | Clock to data wait time | See Figure 2 | 50 | ns | ||
| tCWH | Clock pulse width high | See Figure 2 | 200 | ns | ||
| tCWL | Clock pulse width low | See Figure 2 | 200 | ns | ||
| tCES | Enable to clock setup time | See Figure 2 | 50 | ns | ||
| tEWH | Enable pulse width high | See Figure 2 | 100 | ns | ||
| tCD | Falling clock edge to data wait time | See Figure 2 | 200 | ns | ||
Figure 1. Serial Data Input Timing Diagram There are several other considerations for writing on the SPI:
- The R/W bit must be set to 0.
- The data on SDI pin is clocked into a shift register on each rising edge on the SCK pin.
- The CSB must be held low for data to be clocked. Device will ignore clock pulses if CSB is held high.
- The CSB transition from high to low must occur when SCK is low.
- When SCK and SDI lines are shared between devices, TI recommends hold the CSB line high on the device that is not to be clocked.
There are several other considerations for SPI readback:
- The R/W bit must be set to 1.
- The MUXout pin will always be low for the address portion of the transaction.
- The data on MUXout becomes available momentarily after the falling edge of SCK and therefore should be read back on the rising edge of SCK.
- The data portion of the transition on the SDI line is always ignored.