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ZHCSIC4C June 2018 – November 2018 LMX2615-SP

PRODUCTION DATA.

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

HBD|64
- MCSF001

散熱焊盤(pán)機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購(gòu)信息

6.5 Electrical Characteristics

3.2 V ≤ V_CC ≤ 3.45 V, –55°C ≤ T_C ≤+125°C. Typical values are at V_CC = 3.3 V, 25°C (unless otherwise noted).

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
POWER SUPPLY
V_CC	Supply voltage			3.2	3.3	3.45	V
I_CC	Supply current	OUTA_PD = 0, OUTB_PD = 1 OUTA_MUX = OUTB_MUX = 1 OUTA_PWR = 31, CPG=7 f_OSC= f_PD = 100 MHz, f_VCO = f_OUT = 14.5 GHz			360		mA
	Power on reset current	RESET=1			289
	Power down current	POWERDOWN=1			6
OUTPUT CHARACTERISTICS
p_OUT	Single-ended output power⁽²⁾⁽⁴⁾	50-Ω resistor pullup OUTx_PWR = 31	f_OUT = 8 GHz		6		dBm
p_OUT	Single-ended output power⁽²⁾⁽⁴⁾	50-Ω resistor pullup OUTx_PWR = 31	f_OUT = 15 GHz		4		dBm
INPUT SIGNAL PATH
f_OSCin	Reference input frequency	OSC_2X = 0		5		1000	MHz
f_OSCin	Reference input frequency	OSC_2X = 1		5		200
v_OSCin	Reference input voltage	Single-ended AC coupled sine wave input with complementary side AC coupled to ground with 50 Ω resistor	f_OSCin≥ 20 MHz	0.4		2	Vpp
			10 MHz ≤ f_OSCin <20 MHz	0.8		2
			5 MHz ≤ f_OSCin <10 MHz	1.6		2
PHASE DETECTOR AND CHARGE PUMP
f_PD	Phase detector frequency⁽¹⁾	MASH_ORDER=0		0.125		250	MHz
f_PD	Phase detector frequency⁽¹⁾	MASH_ORDER>0		5		200	MHz
I_CPout	Charge-pump leakage current	CPG = 0				15	nA
	Effective charge pump current. This is the sum of the up and down currents	CPG = 4			3		mA
		CPG = 1			6
		CPG = 5			9
		CPG = 3			12
		CPG = 7			15
PN_{PLL_1/f}	Normalized PLL 1/f noise	f_PD = 100 MHz, f_VCO = 12 GHz⁽³⁾			–129		dBc/Hz
PN_{PLL_FOM}	Normalized PLL noise floor	f_PD = 100 MHz, f_VCO = 12 GHz⁽³⁾			–236		dBc/Hz
VCO CHARACTERISTICS
PN_VCO	VCO phase noise	VCO1 f_VCO = 8.1 GHz	100 kHz		-105		dBc/Hz
			1 MHz		-127
			10 MHz		-148
			100 MHz		-155
		VCO2 f_VCO = 9.3 GHz	100 kHz		-103
			1 MHz		-125
			10 MHz		-146
			100 MHz		-153
		VCO3 f_VCO = 10.4 GHz	100 kHz		-103
			1 MHz		-125
			10 MHz		-147
			100 MHz		-158
		VCO4 f_VCO = 11.4 GHz	100 kHz		-101
			1 MHz		-124
			10 MHz		-146
			100 MHz		-158
		VCO5 f_VCO = 12.5 GHz	100 kHz		-102
			1 MHz		-126
			10 MHz		-147
			100 MHz		-156
		VCO6 f_VCO = 13.6 GHz	100 kHz		-101
			1 MHz		-124
			10 MHz		-146
			100 MHz		-160
		VCO7 f_VCO = 14.7 GHz	100 kHz		-101
			1 MHz		-124
			10 MHz		-146
			100 MHz		-157
t_VCOCAL	VCO calibration speed, switch across the entire frequency band, f_OSC = 100 MHz, f_PD = 100 MHz, f_VCO = 7.9 GHz,VCO_SEL=7	Partial assist			650		µs
K_VCO	VCO Gain	8.1 GHz			94		MHz/V
		9.3 GHz			106
		10.4 GHz			122
		11.4 GHz			148
		12.5 GHz			185
		13.6 GHz			202
		14.7 GHz			233
\|ΔT_CL\|	Allowable temperature drift when VCO is not re-calibrated				125		°C
H2	VCO second harmonic	f_VCO = 8 GHz, divider disabled			–30		dBc
H3	VCO third haromonic	f_VCO = 8 GHz, divider disabled			-25		dBc
DIGITAL INTERFACE Applies to SCLK, SDI, CSB, CAL, RECAL_EN, MUXout, SYNC, SysRefReq
V_IH	High-level input voltage					1.6	V
V_IL	Low-level input voltage			0.4			V
I_IH	High-level input current			–100		100	µA
I_IL	Low-level input current			–100		100	µA
V_OH	High-level output voltage	MUXout pin	Load current = –5 mA	V_CC – 0.6			V
V_OL	High-level output current	MUXout pin	Load current = 5 mA			0.6	V

(1) For lower VCO frequencies, the N divider minimum value canlimit the phase-detector frequency.

(2) Single ended output power obtained after de-embeddingmicrostrip trace losses and matching with a manual tuner. Unused port terminated to 50-Ωload.

(3) The PLL noise contribution is measured using a clean referenceand a wide loop bandwidth and is composed into flicker and flat components. PLL_flat = PLL_FOM + 20× log(Fvco/Fpd) + 10 × log(Fpd / 1Hz). PLL_flicker (offset) = PLL_1/f + 20 × log(Fvco / 1GHz) – 10× log(offset / 10kHz). Once these two components are found, the total PLL noise can be calculatedas PLL_Noise = 10 × log(10 ^{PLL_Flat / 10} + 10 ^{PLL_flicker /10} )

(4) Output power, spurs, and harmonics can vary based on boardlayout and components.