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ZHCSEB9A October 2015 – November 2015 LMK61PD0A2

PRODUCTION DATA.

封裝選項

機械數(shù)據(jù) (封裝 | 引腳)

SIA|8
- MPSI062A

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

訂購信息

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
VDD	Device Supply Voltage	-0.3	3.6	V
V_IN	Output Voltage Range for Logic Inputs	-0.3	VDD + 0.3	V
V_OUT	Output Voltage Range for Clock Outputs	-0.3	VDD + 0.3	V
T_J	Junction Temperature		150	°C
T_STG	Storage Temperature	-40	125	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±4000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1500	V

(1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
VDD	Device Supply Voltage	3.135	3.3	3.465	V
T_A	Ambient Temperature	-40	25	85	°C
T_J	Junction Temperature			125	°C
t_RAMP	VDD Power-Up Ramp Time	0.1		100	ms

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		LMK61PD0A2 ⁽²⁾ ⁽³⁾ ⁽⁴⁾			UNIT
		QFM (SIA)
		8 PINS
		Airflow (LFM) 0	Airflow (LFM) 200	Airflow (LFM) 400
R_θJA	Junction-to-ambient thermal resistance	54	44	41.2	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	34	n/a	n/a
R_θJB	Junction-to-board thermal resistance	36.7	n/a	n/a
ψ_JT	Junction-to-top characterization parameter	11.2	16.9	21.9
ψ_JB	Junction-to-board characterization parameter	36.7	37.8	38.9
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	n/a	n/a	n/a

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

(2) The package thermal resistance is calculated on a 4 layer JEDEC board.

(3) Connected to GND with 3 thermal vias (0.3-mm diameter).

(4) ψJB (junction to board) is used when the main heat flow is from the junction to the GND pad. Please refer to Thermal Considerations section for more information on ensuring good system reliability and quality.

7.5 Electrical Characteristics - Power Supply⁽¹⁾

VDD = 3.3 V ± 5%, T_A = -40C to 85°C

PARAMETER		TEST CONDITIONS	TYP	MAX	UNIT
IDD	Device Current Consumption	LVPECL⁽²⁾	162	208	mA
		LVDS	152	196
		HCSL	155	196
IDD-PD	Device Current Consumption when output is disabled	OE = GND	136

(1) Refer to Parameter Measurement Information for relevant test conditions.

(2) On-chip power dissipation should exclude 40 mW, dissipated in the 150 ohm termination resistors, from total power dissipation.

7.6 LVPECL Output Characteristics⁽¹⁾

VDD = 3.3 V ± 5%, T_A = -40C to 85°C

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
f_OUT	Output Frequency⁽²⁾		62.5		312.5	MHz
V_OD	Output Voltage Swing (V_OH - V_OL)⁽²⁾		700	800	1200	mV
V_{OUT, DIFF, PP}	Differential Output Peak-to-Peak Swing			2 x \|V_OD\|		V
V_OS	Output Common Mode Voltage			VDD – 1.55		V
t_R / t_F	Output Rise/Fall Time (20% to 80%)⁽³⁾			120	200	ps
PN-Floor	Output Phase Noise Floor (f_OFFSET > 10 MHz)	156.25 MHz		-165		dBc/Hz
ODC	Output Duty Cycle⁽³⁾		45%		55%

(1) Refer to Parameter Measurement Information for relevant test conditions.

(2) An output frequency over f_OUT max spec is possible, but output swing may be less than V_OD min spec.

(3) Ensured by characterization.

7.7 LVDS Output Characteristics⁽¹⁾

VDD = 3.3 V ± 5%, T_A = -40°C to 85°C

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
f_OUT	Output Frequency⁽¹⁾		62.5		312.5	MHz
V_OD	Output Voltage Swing (V_OH - V_OL)⁽¹⁾		300	390	480	mV
V_{OUT, DIFF, PP}	Differential Output Peak-to-Peak Swing			2 x \|V_OD\|		V
V_OS	Output Common Mode Voltage			1.2		V
t_R / t_F	Output Rise/Fall Time (20% to 80%)⁽²⁾			150	250	ps
PN-Floor	Output Phase Noise Floor (f_OFFSET > 10 MHz)	156.25 MHz		-162		dBc/Hz
ODC	Output Duty Cycle⁽²⁾		45%		55%
R_OUT	Differential Output Impedance			125		Ohm

(1) An output frequency over f_OUT max spec is possible, but output swing may be less than V_OD min spec.

(2) Ensured by characterization.

7.8 HCSL Output Characteristics⁽¹⁾

VDD = 3.3 V ± 5%, T_A = -40°C to 85°C

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
f_OUT	Output Frequency		62.5		312.5	MHz
V_OH	Output High Voltage		600		850	mV
V_OL	Output Low Voltage		-100		100	mV
V_CROSS	Absolute Crossing Voltage⁽²⁾⁽³⁾		250		475	mV
V_CROSS-DELTA	Variation of V_CROSS⁽²⁾⁽³⁾		0		140	mV
dV/dt	Slew Rate⁽⁴⁾		0.8		2	V/ns
PN-Floor	Output Phase Noise Floor (f_OFFSET > 10 MHz)	100 MHz		-164		dBc/Hz
ODC	Output Duty Cycle⁽⁴⁾		45%		55%

(1) Refer to Parameter Measurement Information for relevant test conditions.

(2) Measured from -150 mV to +150 mV on the differential waveform with the 300 mVpp measurement window centered on the differential zero crossing.

(3) Ensured by design.

(4) Ensured by characterization.

7.9 OE Input Characteristics

VDD = 3.3 V ± 5%, T_A = -40°C to 85°C

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_IH	Input High Voltage		1.4			V
V_IL	Input Low Voltage				0.6	V
I_IH	Input High Current	V_IH = VDD	-40		40	uA
I_IL	Input Low Current	V_IL = GND	-40		40	uA
C_IN	Input Capacitance			2		pF

7.10 OS, FS[1:0] Input Characteristics

VDD = 3.3 V ± 5%, T_A = -40°C to 85°C

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_IH	Input High Voltage		1.4			V
V_IL	Input Low Voltage				0.4	V
I_IH	Input High Current	V_IH = VDD	-40		40	uA
I_IL	Input Low Current	V_IL = GND	-40		40	uA
C_IN	Input Capacitance			2		pF

7.11 Frequency Tolerance Characteristics⁽¹⁾

VDD = 3.3 V ± 5%, T_A = -40°C to 85°C

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
f_T	Total Frequency Tolerance	All output formats, frequency bands and device junction temperature up to 125°C; includes initial freq tolerance, temperature & supply voltage variation, solder reflow and aging (10 years)	-50		50	ppm

(1) Ensured by characterization.

7.12 Power-On/Reset Characteristics (VDD)

VDD = 3.3 V ± 5%, T_A = -40°C to 85°C

PARAMETER		TEST CONDITIONS	MIN	MAX	UNIT
V_THRESH	Threshold Voltage⁽¹⁾		2.72	2.95	V
V_DROOP	Allowable Voltage Droop⁽²⁾			0.1	V
t_STARTUP	Startup Time ⁽¹⁾	Time elapsed from VDD at 3.135 V to output enabled		10	ms
t_OE-EN	Output enable time⁽²⁾	Time elapsed from OE at V_IH to output enabled		50	us
t_OE-DIS	Output disable time⁽²⁾	Time elapsed from OE at V_IL to output disabled		50	us

(1) Ensured by characterization.

(2) Ensured by design.

7.13 PSRR Characteristics⁽¹⁾

VDD = 3.3 V, T_A = 25°C, FS[1:0] = NC, NC

PARAMETER		TEST CONDITIONS	TYP	UNIT
PSRR	Spurs Induced by 50 mV Power Supply Ripple⁽²⁾⁽³⁾ at 156.25 MHz output, all output types	Sine wave at 50 kHz	-70	dBc
		Sine wave at 100 kHz	-70
		Sine wave at 500 kHz	-70
		Sine wave at 1 MHz	-70

(1) Refer to Parameter Measurement Information for relevant test conditions.

(2) Measured max spur level with 50 mVpp sinusoidal signal between 50 kHz and 1 MHz applied on VDD pin

(3) DJ_SPUR (ps, pk-pk) = [2*10(SPUR/20) / (π*f_OUT)]*1e6, where PSRR or SPUR in dBc and f_OUT in MHz.

7.14 PLL Clock Output Jitter Characteristics⁽¹⁾⁽³⁾

VDD = 3.3 V ± 5%, T_A = -40°C to 85°C

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
RJ	RMS Phase Jitter⁽²⁾ (12 kHz – 20 MHz) (1 kHz – 5 MHz)	f_OUT ≥ 100 MHz, All output frequencies and output types		100	200	fs RMS
RJ	RMS Phase Jitter⁽²⁾ (12 kHz – 20 MHz) (1 kHz – 5 MHz)	f_OUT = 62.5 MHz, All output frequencies and output types		200	400	fs RMS

(1) Refer to Parameter Measurement Information for relevant test conditions.

(2) Ensured by characterization.

(3) Phase jitter measured with Agilent E5052 signal source analyzer using a differential-to-single ended converter (balun or buffer).

7.15 Additional Reliability and Qualification

PARAMETER	CONDITION / TEST METHOD
Mechanical Shock	MIL-STD-202, Method 213
Mechanical Vibration	MIL-STD-202, Method 204
Moisture Sensitivity Level	J-STD-020, MSL3

7.16 Typical Performance Characteristics

Figure 1. Phase Noise of LVPECL Differential Output at 156.25 MHz with FS[1:0] = NC, NC, OS = GND

Figure 3. Phase Noise of HCSL Differential Output at 156.25 MHz with FS[1:0] = NC, NC, OS = VDD

Figure 5. LVDS Differential Output Swing vs Frequency

Figure 2. Phase Noise of LVDS Differential Output at 156.25 MHz with FS[1:0] = NC, NC, OS = NC

Figure 4. LVPECL Differential Output Swing vs Frequency

Figure 6. HCSL Differential Output Swing vs Frequency

封裝選項

機械數(shù)據(jù) (封裝 | 引腳)

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

訂購信息

7 Specifications

7.1 Absolute Maximum Ratings

7.2 ESD Ratings

7.3 Recommended Operating Conditions

7.4 Thermal Information

7.5 Electrical Characteristics - Power Supply(1)

7.6 LVPECL Output Characteristics(1)

7.7 LVDS Output Characteristics(1)

7.8 HCSL Output Characteristics(1)

7.9 OE Input Characteristics

7.10 OS, FS[1:0] Input Characteristics

7.11 Frequency Tolerance Characteristics(1)

7.12 Power-On/Reset Characteristics (VDD)

7.13 PSRR Characteristics(1)

7.14 PLL Clock Output Jitter Characteristics(1)(3)

7.15 Additional Reliability and Qualification

7.16 Typical Performance Characteristics

7.5 Electrical Characteristics - Power Supply⁽¹⁾

7.6 LVPECL Output Characteristics⁽¹⁾

7.7 LVDS Output Characteristics⁽¹⁾

7.8 HCSL Output Characteristics⁽¹⁾

7.11 Frequency Tolerance Characteristics⁽¹⁾

7.13 PSRR Characteristics⁽¹⁾

7.14 PLL Clock Output Jitter Characteristics⁽¹⁾⁽³⁾