ZHCSAX1F June 2012 – August 2017 LMK04906
PRODUCTION DATA.
| PIN | I/O | TYPE | DESCRIPTION(1) | |
|---|---|---|---|---|
| NAME | NO. | |||
| Vcc13 | 1 | — | PWR | Power Supply for CLKou0 |
| NC | 2, 5, 7, 8, 9, 15, 17, 19 22, 47, 51, 55, 56, 60, 61, 64 |
— | No Connect | These pins must be left floating. |
| CLKout0*, CLKout0 | 3, 4 | O | Programmable | Clock output 0. |
| SYNC / Status_CLKin2 | 6 | I/O | Programmable | CLKout Synchronization input or CLKin2 Status output. |
| Vcc1 | 10 | — | PWR | Power supply for VCO LDO. |
| LDObyp1 | 11 | — | ANLG | LDO Bypass, bypassed to ground with 10 µF capacitor. |
| LDObyp2 | 12 | — | ANLG | LDO Bypass, bypassed to ground with a 0.1 µF capacitor. |
| CLKout1, CLKout1* | 13, 14 | O | Programmable | Clock output 1. |
| Vcc2 | 16 | — | PWR | Power supply for CLKout1. |
| Vcc3 | 18 | — | PWR | Power supply for CLKout2 |
| CLKout2*, CLKout2 | 20, 21 | O | Programmable | Clock output 2 |
| GND | 23 | — | PWR | Ground |
| Vcc4 | 24 | — | PWR | Power supply for digital. |
| CLKin1, CLKin1* | 25, 26 | I | ANLG | Reference Clock Input Port 1 for PLL1. AC or DC Coupled. |
| FBCLKin, FBCLKin* | Feedback input for external clock feedback input (0-delay mode). AC or DC Coupled. | |||
| Fin/Fin* | External VCO input (External VCO mode). AC or DC Coupled. | |||
| Status_Holdover | 27 | I/O | Programmable | Programmable status pin, default readback output. Programmable to holdover mode indicator. Other options available by programming. |
| CLKin0, CLKin0* | 28, 29 | I | ANLG | Reference Clock Input Port 0 for PLL1. AC or DC Coupled. |
| Vcc5 | 30 | — | PWR | Power supply for clock inputs. |
| CLKin2, CLKin2* | 31, 32 | I | ANLG | Reference Clock Input Port 2 for PLL1, AC or DC Coupled. |
| Status_LD | 33 | I/O | Programmable | Programmable status pin, default lock detect for PLL1 and PLL2. Other options available by programming. |
| CPout1 | 34 | O | ANLG | Charge pump 1 output. |
| Vcc6 | 35 | — | PWR | Power supply for PLL1, charge pump 1. |
| OSCin, OSCin* | 36, 37 | I | ANLG | Feedback to PLL1, Reference input to PLL2. AC Coupled. |
| Vcc7 | 38 | — | PWR | Power supply for OSCin port. |
| OSCout0, OSCout0* | 39, 40 | O | Programmable | Buffered output 0 of OSCin port. |
| Vcc8 | 41 | — | PWR | Power supply for PLL2, charge pump 2. |
| CPout2 | 42 | O | ANLG | Charge pump 2 output. |
| Vcc9 | 43 | — | PWR | Power supply for PLL2. |
| LEuWire | 44 | I | CMOS | MICROWIRE Latch Enable Input. |
| CLKuWire | 45 | I | CMOS | MICROWIRE Clock Input. |
| DATAuWire | 46 | I | CMOS | MICROWIRE Data Input. |
| Vcc10 | 48 | — | PWR | Power supply for CLKout3. |
| CLKout3, CLKout3* | 49, 50 | O | Programmable | Clock output 3. |
| Vcc11 | 52 | — | PWR | Power supply for CLKout4. |
| CLKout4, CLKout4* | 53, 54 | O | Programmable | Clock output 4. |
| Vcc12 | 57 | — | PWR | Power supply for CLKout5. |
| CLKout5, CLKout5* | 58, 59 | O | Programmable | Clock output 5. |
| Status_CLKin0 | 62 | I/O | Programmable | Programmable status pin. Default is input for pin control of PLL1 reference clock selection. CLKin0 LOS status and other options available by programming. |
| Status_CLKin1 | 63 | I/O | Programmable | Programmable status pin. Default is input for pin control of PLL1 reference clock selection. CLKin1 LOS status and other options available by programming. |
| DAP | DAP | — | GND | DIE ATTACH PAD, connect to GND. |