4 Revision History
Changes from Revision B (June 2017) to Revision C (July 2021)
- 將數(shù)據(jù)表標(biāo)題從LMK00338 8 路輸出差動(dòng)時(shí)鐘緩沖器和電平轉(zhuǎn)換器 更改為：LMK00338 8 路輸出 PCIe 第 1 代/第 2 代/第 3 代/第 4 代/第 5 代時(shí)鐘緩沖器和電平轉(zhuǎn)換器
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- 更改了目標(biāo)應(yīng)用，方法為將附加應(yīng)用添加到第二個(gè)和第三個(gè)要點(diǎn)，并且從第一個(gè)要點(diǎn)中刪除高速和串行接口。Go
- 在數(shù)據(jù)表中添加了 PCIe 第 5 代Go
- Changed guarantee to ensure throughout.Go
- Added PCIe 4.0 compliance dataGo
- Added additive RMS phase jitter for PCIe 4.0 and PCIe 5.0 to the Electrical
Characteristics tableGo
- Removed the LVPECL Phase Noise at 100 MHz graph Go
- Changed the third paragraph in Driving the Clock Inputs section to include CLKin* and LVCMOS text. Revised to better correspond with information in the Electrical Characteristics tableGo
- Changed the bypass cap text to signal attenuation text of the fourth paragraph in Driving the Clock Inputs section.Go
- Changed the Single-Ended LVCMOS Input, DC Coupling with Common Mode Biasing image with revised graphic.Go
Changes from Revision A (October 2014) to Revision B (June 2017)
- 已將整個(gè)數(shù)據(jù)表中的 CLKoutA_EN 和 CLKoutB_EN 引腳更改為 CLKoutA_EN 和 CLKoutB_EN
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Changes from Revision * (December 2013) to Revision A (October 2014)
- 添加、更新或重命名了以下各個(gè)部分：器件信息表、應(yīng)用和實(shí)施；電源建議；布局；器件和文檔支持；機(jī)械、封裝和可訂購(gòu)信息
Go
- Added PCIE Gen4 additive jitter to the Electrical Characteristics table Go
- Changed 1 MHz to 12 kHz Go
- Added Figure 10-1
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