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ZHCSO08A December 2021 – November 2022 LMH5485-SEP

PRODUCTION DATA

封裝選項

請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。

機(jī)械數(shù)據(jù) (封裝 | 引腳)

DGK|8

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購信息

zhcso08a_oa

7.6 Electrical Characteristics: Vs+ – Vs- = 3 V

at T_A = -55℃ to 125℃, V_OCM = open (defaults midsupply), Vout = 2 V_PP, Rf = 402 Ω, Rload = 499 Ω, 50-Ω input match, G = 2 V/V, single-ended input, differential output, and PD = Vs+, unless otherwise noted. See Figure 8-1 for an AC-coupled gain of a 2-V/V test circuit, and Figure 8-2 for a DC-coupled gain of a 2-V/V test circuit.

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
AC PERFORMANCE
	Small-signal bandwidth	Vout = 100 mV_PP, G = 1			585		MHz
		Vout = 100 mV_PP, G = 2			490		MHz
		Vout = 100 mV_PP, G = 5			180		MHz
GBWP	Gain-bandwidth product	Vout = 100 mV_PP, G = 20			850		MHz
	Large-signal bandwidth	Vout = 2 V_PP			275		MHz
	Bandwidth for 0.1-dB flatness	Vout = 2 V_PP			120		MHz
	Slew rate⁽¹⁾	Vout = 2-V step, FPBW			1200		V/μs
	Rise/fall time	Vout = 2-V step, input ≤ 0.5 ns t_r			1.6		ns
	Settling time	Vout = 2-V step, t_r = 2 ns	To 1%		5		ns
	Settling time	Vout = 2-V step, t_r = 2 ns	To 0.1%		8		ns
	Overshoot and undershoot	Vout = 2-V step, input ≤ 0.3 ns t_r			11%
	100-kHz harmonic distortion	Vout = 2 V_PP	HD2		–118		dBc
	100-kHz harmonic distortion	Vout = 2 V_PP	HD3		–148		dBc
	10-MHz harmonic distortion	Vout = 2 V_PP	HD2		–90		dBc
	10-MHz harmonic distortion	Vout = 2 V_PP	HD3		–100		dBc
	2nd-order intermodulation distortion	f = 10 MHz, 100-kHz tone spacing, Vout envelope = 2 V_PP (1 V_PP per tone)			–89		dBc
	3rd-order intermodulation distortion				–87		dBc
e_n	Input voltage noise	f > 100 kHz			2.4		nV/√Hz
i_n	Input current noise	f > 1 MHz			1.9		pA/√Hz
	Overdrive recovery time	2X output overdrive, either polarity			20		ns
	Closed-loop output impedance	f = 10 MHz (differential)			0.1		Ω
DC PERFORMANCE
A_OL	Open-loop voltage gain			97	119		dB
	Input-referred offset voltage			–900	±100	900	μV
	Input offset voltage drift⁽²⁾			–2.5	±0.5	2.5	μV/°C
	Input bias current	Positive out of node		1.7	9	15	μA
	Input bias current drift⁽²⁾				5	15	nA/°C
	Input offset current			–650	±150	650	nA
	Input offset current drift⁽²⁾			–1.5	±0.3	1.5	nA/°C
INPUT
	Common-mode input low	< 3-dB degradation in CMRR from midsupply			(Vs–) – 0.2	Vs–	V
	Common-mode input high	< 3-dB degradation in CMRR from midsupply		(Vs+) – 1.3	(Vs+) –1.2		V
	Common-mode rejection ratio	Input pins at midsupply		82	100		dB
	Input impedance differential mode	Input pins at midsupply			110 \|\| 0.9		kΩ \|\| pF
OUTPUT
	Output voltage low				(Vs–) + 0.2	(Vs–) + 0.25	V
	Output voltage high			(Vs+) – 0.25	(Vs+) – 0.2		V
	Output current drive			±55	±60		mA
POWER SUPPLY
	Specified operating voltage			2.7	3	5.1	V
	Quiescent operating current			9	9.7	10.6	mA
±PSRR	Power-supply rejection ratio	Either supply pin to differential Vout		82	100		dB
POWER DOWN
	Enable voltage threshold			(Vs–) + 1.7			V
	Disable voltage threshold					(Vs–) + 0.7	V
	Disable pin bias current	PD = Vs– → Vs+			20	50	nA
	Power-down quiescent current	PD = (Vs–) + 0.7 V			2	30	μA
	Power-down quiescent current	PD = Vs–			1	8	μA
	Turnon-time delay	Time from PD = low to Vout = 90% of final value			100		ns
	Turnoff time delay	Time from PD = low to Vout = 10% of final value			60		ns
OUTPUT COMMON-MODE VOLTAGE CONTROL⁽³⁾
	Small-signal bandwidth	V_OCM = 100 mV_PP			140		MHz
	Slew rate⁽¹⁾	V_OCM = 1-V step			350		V/μs
	Gain			0.975	0.987	0.990	V/V
	Input bias current	Considered positive out of node		–0.7	0.1	0.7	μA
	Input impedance	V_OCM input driven to midsupply			47 \|\| 1.2		kΩ \|\| pF
	Default voltage offset from midsupply	V_OCM pin open		–45	±10	45	mV
CM V_OS	Common-mode offset voltage	V_OCM input driven to midsupply		–8	±2	8	mV
	CM V_OS drift⁽²⁾	V_OCM input driven to midsupply		–20	±4	20	μV/°C
	Common-mode loop supply headroom to negative supply	< ±15-mV shift from midsupply CM V_OS		0.94			V
	Common-mode loop supply headroom to positive supply	< ±15-mV shift from midsupply CM V_OS		1.2			V

(1) This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (V_P / √2) × 2π × f_–3dB.

(2) Input offset voltage drift, input bias current drift, input offset current drift, and V_OCM drift are average values calculated by taking data at the at the maximum-range ambient-temperature end-points, computing the difference, and dividing by the temperature range. Maximum drift set by distribution of a large sampling of devices. Drift is not specified by test or QA sample test.

(3) Specifications are from input V_OCM pin to differential output average voltage.