ZHCSK76 September 2019 LM74202-Q1
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Parameter Measurement Information
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Undervoltage Lockout (UVLO)
- 8.3.2 Overvoltage Protection (OVP)
- 8.3.3 Reverse Battery Protection
- 8.3.4 Hot Plug-In and In-Rush Current Control
- 8.3.5 Overload and Short Circuit Protection
- 8.4 Device Functional Modes
-
9 Application and Implementation
- 9.1 Application Information
- 9.2
Typical Application
- 9.2.1 Design Requirements
- 9.2.2 Detailed Design Procedure
- 9.2.3 Application Curves
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機(jī)械、封裝和可訂購信息
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- PWP|16
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- PWP|16
訂購信息
8.3.5.7 Low Current Shutdown Control (SHDN)
The internal FETs and hence the load current can be switched off by pulling the SHDN pin below V(SHUTF) threshold with a micro-controller GPIO pin as shown in Figure 38. The device quiescent current reduces to 16 μA (typical) in shutdown state. To assert SHDN low, the pull down must sink at least 10 µA at 400 mV. To enable the device, SHDN must be pulled up to V(SHUTR) threshold. Once the device is enabled, the internal FETs turns on with dVdT mode.
Figure 38. Shutdown Control