老司机求福利网址2017,亚洲春色在线播放

ZHCSI53A May 2018 – November 2018 LM5122ZA

PRODUCTION DATA.

封裝選項

機械數(shù)據(jù) (封裝 | 引腳)

PWP|24
- MPDS372A

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

PWP|24
- PPTD407

訂購信息

6.5 Electrical Characteristics

Unless otherwise specified, these specifications apply for –40°C ≤ T_J ≤ +125°C, V_VIN = 12 V, V_VCC = 8.3 V, R_T = 20 kΩ, no load on LO and HO. Typical values represent the most likely parametric norm at T_J = 25°C and are provided for reference purposes only.

	PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
VIN SUPPLY
I_SHUTDOWN	VIN shutdown current	V_UVLO = 0 V		9	17	µA
I_BIAS	VIN operating current (exclude the current into RT resistor)	V_UVLO = 2 V, non-switching		4	5	mA
VCC REGULATOR
V_CC(REG)	VCC regulation	No load	6.9	7.6	8.3	V
	VCC dropout (VIN to VCC)	V_VIN = 4.5 V, no external load			0.25	V
	VCC dropout (VIN to VCC)	V_VIN = 4.5 V, I_VCC = 25 mA		0.28	0.5	V
	VCC sourcing current limit	V_VCC = 0 V	50	62		mA
I_VCC	VCC operating current (exclude the current into RT resistor)	V_VCC = 8.3 V		3.5	5	mA
I_VCC		V_VCC = 12 V		4.5	8	mA
	VCC undervoltage threshold	VCC rising, V_VIN = 4.5 V	3.9	4	4.1	V
	VCC undervoltage threshold	VCC falling, V_VIN = 4.5 V			3.7	V
	VCC undervoltage hysteresis			0.385		V
UNDERVOLTAGE LOCKOUT
	UVLO threshold	UVLO rising	1.17	1.2	1.23	V
	UVLO hysteresis current	V_UVLO = 1.4 V	7	10	13	µA
	UVLO standby enable threshold	UVLO rising	0.3	0.4	0.5	V
	UVLO standby enable hysteresis			0.1	0.125	V
MODE
	Diode emulation mode threshold	MODE rising	1.2	1.24	1.28	V
	Diode emulation mode hysteresis			0.1		V
	Default MODE voltage		145	155	170	mV
	Default skip cycle threshold	COMP rising, measured at COMP		1.290		V
	Default skip cycle threshold	COMP falling, measured at COMP		1.245		V
	Skip cycle hysteresis	Measured at COMP		40		mV
ERROR AMPLIFIER
V_REF	FB reference voltage	Measured at FB, V_FB = V_COMP	1.188	1.2	1.212	V
	FB input bias current	V_FB = V_REF		5		nA
V_OH	COMP output high voltage	I_SOURCE = 2 mA, V_VCC = 4.5 V	2.75			V
V_OH	COMP output high voltage	I_SOURCE = 2 mA, V_VCC = 12 V	3.4			V
V_OL	COMP output low voltage	I_SINK = 2 mA			0.25	V
A_OL	DC gain			80		dB
f_BW	Unity gain bandwidth			3		MHz
	Slave mode threshold	FB rising		2.7	3.4	V
OSCILLATOR
f_SW1	Switching frequency 1	R_T = 20 kΩ	400	450	500	kHz
f_SW2	Switching frequency 2	R_T = 10 kΩ	775	875	975	kHz
	RT output voltage			1.2		V
	RT sync rising threshold	RT rising		2.5	2.9	V
	RT sync falling threshold	RT falling	1.6	2		V
	Minimum sync pulse width		100			ns
SYNCOUT
	SYNCOUT high-state voltage	I_SYNCOUT = –1 mA	3.3	4.3		V
	SYNCOUT low-state voltage	I_SYNCOUT = 1 mA		0.15	0.25	V
OPT
	Synchronization selection threshold	OPT rising	2	3	4	V
SLOPE COMPENSATION
	SLOPE output voltage		1.17	1.2	1.23	V
V_SLOPE	Slope compensation amplitude	R_SLOPE = 20 kΩ, f_SW = 100 kHz, 50% duty cycle, T_J = –40°C to 125°C	1.375	1.65	1.925	V
V_SLOPE	Slope compensation amplitude	R_SLOPE= 20 kΩ, f_SW= 100 kHz, 50% duty cycle, T_J = 25°C	1.4	1.65	1.9	V
SOFT START
I_SS-SOURCE	SS current source	V_SS = 0 V	7.5	10	12	µA
	SS discharge switch R_DS-ON			13		Ω
PWM COMPARATOR
t_LO-OFF	Forced LO off-time	V_VCC = 5.5 V		330	400	ns
t_LO-OFF	Forced LO off-time	V_VCC = 4.5 V		560	750	ns
t_ON-MIN	Minimum LO on-time	R_SLOPE = 20 kΩ		150		ns
t_ON-MIN	Minimum LO on-time	R_SLOPE = 200 kΩ		300		ns
	COMP to PWM voltage drop	T_J = –40°C to 125°C	0.95	1.1	1.25	V
	COMP to PWM voltage drop	T_J = 25°C	1	1.1	1.2	V
CURRENT SENSE / CYCLE-BY-CYCLE CURRENT LIMIT
V_CS-TH1	Cycle-by-cycle current limit threshold	CSP to CSN, T_J = –40°C to 125°C	65.5	75	87.5	mV
V_CS-TH1	Cycle-by-cycle current limit threshold	CSP to CSN, T_J = 25°C	67	75	86	mV
V_CS-ZCD	Zero cross detection threshold	CSP to CSN, rising		7		mV
V_CS-ZCD	Zero cross detection threshold	CSP to CSN, falling	0.5	6	12	mV
	Current sense amplifier gain			10		V/V
I_CSP	CSP input bias current			12		µA
I_CSN	CSN input bias current			11		µA
	Bias current matching	I_CSP – I_CSN	–2.5	1	8.75	µA
	CS to LO delay	Current sense / current limit delay		150		ns
HICCUP-MODE RESTART
V_RES	Restart threshold	RES rising	1.15	1.2	1.25	V
V_HCP-UPPER	Hiccup counter upper threshold	RES rising		4.2		V
V_HCP-UPPER	Hiccup counter upper threshold	RES rising, V_VIN = V_VCC = 4.5 V		3.6		V
V_HCP-LOWER	Hiccup counter lower threshold	RES falling		2.15		V
V_HCP-LOWER	Hiccup counter lower threshold	RES falling, V_VIN = V_VCC = 4.5 V		1.85		V
I_RES-SOURCE1	RES current source1	Fault-state charging current	20	30	40	µA
I_RES-SINK1	RES current sink1	Normal-state discharging current		5		µA
I_RES-SOURCE2	RES current source2	Hiccup-mode off-time charging current		10		µA
I_RES-SINK2	RES current sink2	Hiccup-mode off-time discharging current		5		µA
	Hiccup cycle			8		Cycles
	RES discharge switch R_DS-ON			40		Ω
	Ratio of hiccup mode off-time to restart delay time			122
HO GATE DRIVER
V_OHH	HO high-state voltage drop	I_HO = –100 mA, V_OHH = V_BST –V_HO		0.15	0.24	V
V_OLH	HO low-state voltage drop	I_HO = 100 mA, V_OLH = V_HO –V_SW		0.1	0.18	V
	HO rise time (10% to 90%)	C_LOAD = 4700 pF, V_BST = 12 V		25		ns
	HO fall time (90% to 10%)	C_LOAD = 4700 pF, V_BST = 12 V		20		ns
I_OHH	Peak HO source current	V_HO = 0 V, V_SW = 0 V, V_BST = 4.5 V		0.8		A
I_OHH	Peak HO source current	V_HO = 0 V, V_SW = 0 V, V_BST = 7.6 V		1.9		A
I_OLH	Peak HO sink current	V_HO = V_BST = 4.5 V		1.9		A
I_OLH	Peak HO sink current	V_HO = V_BST= 7.6 V		3.2		A
I_BST	BST charge pump sourcing current	V_VIN = V_SW = 9. V , V_BST - V_SW = 5 V	100	200		µA
	BST charge pump regulation	B_ST to SW, I_BST= –70 μA, V_VIN = V_SW = 9 V	5.3	6.2	6.75	V
	BST charge pump regulation	B_ST to SW, I_BST = –70 μA, V_VIN = V_SW = 12 V	7	8.5	9	V
	BST to SW undervoltage		2	3	3.5	V
	BST DC bias current	V_BST – V_SW = 12 V, V_SW = 0 V		30	45	µA
LO GATE DRIVER
V_OHL	LO high-state voltage drop	I_LO = –100 mA, V_OHL = V_VCC –V_LO		0.15	0.25	V
V_OLL	LO low-state voltage drop	I_LO = 100 mA, V_OLL = V_LO		0.1	0.17	V
	LO rise time (10% to 90%)	C_LOAD = 4700 pF		25		ns
	LO fall time (90% to 10%)	C_LOAD = 4700 pF		20		ns
I_OHL	Peak LO source current	V_LO= 0 V, V_VCC = 4.5 V		0.8		A
I_OHL	Peak LO source current	V_LO = 0 V		2		A
I_OLL	Peak LO sink current	V_LO = V_VCC = 4.5 V		1.8		A
I_OLL	Peak LO sink current	V_LO = V_VCC		3.2		A
SWITCHING CHARACTERISTICS
t_DLH	LO fall to HO rise delay	No load, 50% to 50%	50	80	145	ns
t_DHL	HO fall to LO rise delay	No load, 50% to 50%	60	80	105	ns
THERMAL
T_SD	Thermal shutdown	Temperature rising		165		°C
	Thermal shutdown hysteresis			25		°C