9.3.1 Current Limit

The current limit threshold is reached when the voltage across the sense resistor R_SNS (VIN_K to SENSE) exceeds the ILIM threshold (26 mV if CL = VDD and 50 mV if CL = GND). In the current limiting condition, the GATE voltage is controlled to limit the current in MOSFET Q₁. While the current limit circuit is active, the fault timer is active as described in the Fault Timer and Restart section. If the load current falls below the current limit threshold before the end of the Fault Timeout Period, the LM5066 resumes usual operation. If the current limit condition persists for longer than the Fault Timeout Period set by C_T, the IIN OC Fault bit in the STATUS_INPUT (7Ch) register, the INPUT bit in the STATUS_WORD (79h) register, and IIN_OC/PFET_OP_FAULT bit in the DIAGNOSTIC_WORD (E1h) register is toggled high and SMBA pin is asserted. SMBA toggling can be disabled using the ALERT_MASK (D8h) register. For proper operation, the R_SNS resistor value should be no higher than 200 mΩ. Higher values may create instability in the current limit control loop. The current limit threshold pin value may be overridden by setting appropriate bits in the DEVICE_SETUP register (D9h).

9.3.2 Circuit Breaker

If the load current increases rapidly (for example, the load is short circuited), the current in the sense resistor (R_S) may exceed the current limit threshold before the current limit control loop is able to respond. If the current exceeds 1.94x or 3.87x (CL = GND) the current limit threshold, Q₁ is quickly switched off by the 160-mA pulldown current at the GATE pin and a Fault Timeout Period begins. When the voltage across R_SNS falls below the circuit breaker (CB) threshold, the 115-mA pulldown current at the GATE pin is switched off, and the gate voltage of Q₁ is then determined by the current limit or the power limit functions. If the TIMER pin reaches 3.9 V before the current limiting or power limiting condition ceases, Q₁ is switched off by the 4.2-mA pulldown current at the GATE pin as described in the Fault Timer and Restart section. A circuit breaker event causes the CIRCUIT BREAKER FAULT bit in the STATUS_OTHER (7Fh), STATUS_MFR_SPECIFIC (80h), and DIAGNOSTIC_WORD (E1h) registers to be toggled high and SMBA pin are asserted unless this feature is disabled using the ALERT_MASK (D8h) register. The circuit breaker pin configuration may be overridden by setting appropriate bits in the DEVICE_SETUP (D9h) register.

9.3.3 Power Limit

An important feature of the LM5066 is the MOSFET power limiting. The Power Limit function can be used to maintain the maximum power dissipation of MOSFET Q₁ within the device SOA rating. The LM5066 determines the power dissipation in Q₁ by monitoring its drain-source voltage (SENSE to OUT), and the drain current through the R_SNS (VIN_K to SENSE). The product of the current and voltage is compared to the power limit threshold programmed by the resistor at the PWR pin. If the power dissipation reaches the limiting threshold, the GATE voltage is modulated to regulate the current in Q₁. While the power limiting circuit is active, the fault timer is active as described in the Fault Timer and Restart section. If the power limit condition persists for longer than the Fault Timeout Period set by the timer capacitor, C_T, the IIN OC Fault bit in the STATUS_INPUT (7Ch) register, the INPUT bit in the STATUS_WORD (79h) register, and the IIN_OC/PFET_OP_FAULT bit in the DIAGNOSTIC_WORD (E1h) register is toggled high and SMBA pin is asserted unless this feature is disabled using the ALERT_MASK (D8h) register.

9.3.4 UVLO

The series-pass MOSFET (Q₁) is enabled when the input supply voltage (V_IN) is within the operating range defined by the programmable UVLO and OVLO levels. Typically the UVLO level at V_IN is set with a resistor divider. Referring to the Functional Block Diagram when V_IN is below the UVLO level, the internal 20-µA current source at UVLO is enabled, the current source at OVLO is off, and Q₁ is held off by the 4.2-mA pulldown current at the GATE pin. As V_IN is increased, raising the voltage at UVLO above its threshold the 20 µA current source at UVLO is switched off, increasing the voltage at UVLO, providing hysteresis for this threshold. With the UVLO/EN pin above its threshold, Q₁ is switched on by the 20-µA current source at the GATE pin if the insertion time delay has expired.

See the Application and Implementation section for a procedure to calculate the values of the threshold setting resistors. The minimum possible UVLO level at V_IN can be set by connecting the UVLO/EN pin to VIN. In this case, Q₁ is enabled after the insertion time when the voltage at VIN reaches the POR threshold. After power-up, an UVLO condition causes the INPUT bit in the STATUS_WORD (79h) register, the VIN_UV_FAULT bit in the STATUS_INPUT (7Ch) register, and the VIN_UNDERVOLTAGE_FAULT bit in the DIAGNOSTIC_WORD (E1h) registers to be toggled high and SMBA pin is pulled low unless this feature is disabled using the ALERT_MASK (D8h) register.

9.3.5 OVLO

The series-pass MOSFET (Q₁) is enabled when the input supply voltage (V_IN) is within the operating range defined by the programmable UVLO and OVLO levels. If V_IN raises the OVLO pin voltage above its threshold, Q₁ is switched off by the 4.2-mA pulldown current at the GATE pin, denying power to the load. When the OVLO pin is above its threshold, the internal 21-µA current source at OVLO is switched on, raising the voltage at OVLO to provide threshold hysteresis. When V_IN is reduced below the OVLO level Q₁ is re-enabled. An OVLO condition toggles the VIN_OV_FAULT bit in the STATUS_INPUT (7Ch) register, the INPUT bit in the STATUS_WORD (79h) register and the VIN_OVERVOLTAGE_FAULT bit in the DIAGNOSTIC_WORD (E1h) register. The SMBA pin is pulled low unless this feature is disabled using the ALERT_MASK (D8h) register.

See the Application and Implementation section for a procedure to calculate the threshold setting resistor values.

9.3.6 Power Good Pin

The Power Good indicator pin (PGD) is connected to the drain of an internal N-channel MOSFET capable of sustaining 80 V in the off-state, and transients up to 100 V. An external pullup resistor is required at PGD to an appropriate voltage to indicate the status to downstream circuitry. The off-state voltage at the PGD pin can be higher or lower than the voltages at VIN and OUT. PGD is switched high when the voltage at the FB pin exceeds the PGD threshold voltage. Typically, the output voltage threshold is set with a resistor divider from output to feedback, although the monitored voltage need not be the output voltage. Any other voltage can be monitored as long as the voltage at the FB pin does not exceed its maximum rating. Referring to the Functional Block Diagram, when the voltage at the FB pin is below its threshold, the 20-µA current source at FB is disabled. As the output voltage increases, taking FB above its threshold, the current source is enabled, sourcing current out of the pin, raising the voltage at FB to provide threshold hysteresis. The PGD output is forced low when either the UVLO/EN pin is below its threshold or the OVLO pin is above its threshold. The status of the PGD pin can be read through the PMBus interface in either the STATUS_WORD (79h) or DIAGNOSTIC_WORD (E1h) registers.

9.3.7 VDD Sub-Regulator

The LM5066 contains an internal linear sub-regulator, which steps down the input voltage to generate a 4.9-V rail used for powering low voltage circuitry. The VDD sub-regulator should be used as the pullup supply for the CL, RETRY, ADR2, ADR1, and ADR0 pins if they are to be tied high. It may also be used as the pullup supply for the PGD and the SMBus signals (SDA, SCL, and SMBA). The VDD sub-regulator is not designed to drive high currents and should not be loaded with other integrated circuits. The VDD pin is current limited to 30 mA in order to protect the LM5066 in the event of a short. The sub-regulator requires a ceramic bypass capacitance having a value of 1 µF or greater to be placed as close to the VDD pin as the PCB layout allows.

9.3.8 Remote Temperature Sensing

The LM5066 is designed to measure temperature remotely using an MMBT3904 NPN transistor. The base and collector of the MMBT3904 should be connected to the DIODE pin and the emitter to the LM5066 ground. Place the MMBT3904 near the device that requires temperature sensing. If the temperature of the hot swap pass MOSFET, Q₁, is to be measured, the MMBT3904 should be placed as close to Q₁ as the layout allows. The temperature is measured by means of a change in the diode voltage in response to a step in current supplied by the DIODE pin. The DIODE pin sources a constant 9.4 µA, but pulses 250 µA once every millisecond to measure the diode temperature. Take care in the PCB layout to keep the parasitic resistance between the DIODE pin and the MMBT3904 low so as not to degrade the measurement. In addition it is recommended to make a Kelvin connection from the emitter of the MMBT3904 to the GND of the part to ensure an accurate measurement. Additionally, a small 1000-pF bypass capacitor should be placed in parallel with the MMBT3904 to reduce the effects of noise. The temperature can be read using the READ_TEMPERATURE_1 PMBus command (8Dh). The default limits of the LM5066 causes SMBA pin to be pulled low if the measured temperature exceeds 125°C and disables Q₁ if the temperature exceeds 150°C. These thresholds can be reprogrammed through the PMBus interface using the OT_WARN_LIMIT (51h) and OT_FAULT_LIMIT (4Fh) commands. If the temperature measurement and protection capability of the LM5066 are not used, the DIODE pin should be grounded.

Erroneous temperature measurements may result when the device input voltage is below the minimum operating voltage (10 V), due to VREF dropping out below the nominal voltage (2.97 V). At higher ambient temperatures, this measurement could read a value higher than the OT_FAULT_LIMIT, and trigger a fault, disabling Q₁. In this case, the faults should be removed and the device reset by writing a 0h, followed by an 80h to the OPERATION (03h) register.

9.3.9 Damaged MOSFET Detection

The LM5066 is able to detect whether the external MOSFET, Q₁, is damaged under certain conditions. If the voltage across the sense resistor exceeds 4 mV while the GATE voltage is low or the internal logic indicates that the GATE should be low, the EXT_MOSFET_SHORTED bit in the STATUS_MFR_SPECIFIC (80h) and DIAGNOSTIC_WORD (E1h) registers are toggled high and the SMBA pin is asserted unless this feature is disabled using the ALERT_MASK register (D8h). This method effectively determines whether Q₁ is shorted because of damage present between the drain and gate and/or drain and source.

9.4.1 Power-Up Sequence

The VIN operating range of the LM5066 is 10 to 80 V, with a transient capability to 100 V. Referring to the 簡(jiǎn)化電路原理圖 and Figure 22, as the voltage at VIN initially increases, the external N-channel MOSFET (Q₁) is held off by an internal 115-mA pulldown current at the GATE pin. The strong pulldown current at the GATE pin prevents an inadvertent turn-on as the gate-to-drain (Miller) capacitance of the MOSFET is charged. Additionally, the TIMER pin is initially held at ground. When the V_IN voltage reaches the POR threshold the insertion time begins. During the insertion time, the capacitor at the TIMER pin (C_T) is charged by a 4.8-µA current source, and Q₁ is held off by a 4.2-mA pulldown current at the GATE pin regardless of the input voltage. The insertion time delay allows ringing and transients at V_IN to settle before Q₁ is enabled. The insertion time ends when the TIMER pin voltage reaches 3.9 V. C_T is then quickly discharged by an internal 1.5-mA pulldown current. The GATE pin then switches on Q₁ when V_IN exceeds the UVLO threshold. If V_IN is above the UVLO threshold at the end of the insertion time, Q₁ the GATE pin charge pump sources 20 µA to charge the gate capacitance of Q₁. The maximum voltage from the gate to source of the Q₁ is limited by an internal 16.5-V Zener diode.

As the voltage at the OUT pin increases, the LM5066 monitors the drain current and power dissipation of MOSFET Q₁. In-rush current limiting or power limiting circuits, or both, actively control the current delivered to the load. During the in-rush limiting interval (t₂ in Figure 22), an internal 75-µA fault timer current source charges C_T. If Q₁’s power dissipation and the input current reduce below their respective limiting thresholds before the TIMER pin reaches 3.9 V, the 75-µA current source is switched off, and C_T is discharged by the internal 2.5-µA current sink (t₃ in Figure 22). The in-rush limiting no longer engages unless a current-limit condition occurs.

If the TIMER pin voltage reaches 3.9 V before in-rush current limiting or power limiting ceases during t₂, a fault is declared and Q₁ is turned off. See the Fault Timer and Restart section for a complete description of the fault mode.

The LM5066 asserts the SMBA pin after the input voltage has exceeded its POR threshold to indicate that the volatile memory and device settings are in their default state. The CONFIG_PRESET bit within the STATUS_MFR_SPECIFIC register (80h) indicates default configuration of warning thresholds and device operation and remains high until a CLEAR_FAULTS command is received.

Figure 22. Power-Up Sequence (Current Limit Only)

9.4.2 Gate Control

A charge pump provides the voltage at the GATE pin to enhance the N-channel MOSFET’s gate (Q₁). During normal operating conditions (t₃ in Figure 22), the gate of Q₁ is held charged by an internal 20-µA current source. The charge pump peak voltage is roughly 13.5 V, which forces a V_GS across Q1 of 13.5 V under normal operation. When the system voltage is initially applied, the GATE pin is held low by a 115-mA pulldown current. This helps prevent an inadvertent turn-on of Q₁ through its drain-gate capacitance as the applied system voltage increases.

During the insertion time (t₁ in Figure 22) the GATE pin is held low by a 4.2-mA pulldown current. This maintains Q₁ in the off-state until the end of t₁, regardless of the voltage at VIN or UVLO. Following the insertion time, during t₂ in Figure 22 the gate voltage of Q₁ is modulated to keep the current or power dissipation level from exceeding the programmed levels. While in the current or power limiting mode, the TIMER pin capacitor is charging. If the current and power limiting cease before the TIMER pin reaches 3.9 V, the TIMER pin capacitor then discharges, and the circuit begins normal operation. If the in-rush limiting condition persists such that the TIMER pin reached 3.9 V during t₂, the GATE pin is then pulled low by the 4.2-mA pulldown current. The GATE pin is then held low until either a power-up sequence is initiated (RETRY pin to VDD), or an automatic retry is attempted (RETRY pin to GROUND or floating). See the Fault Timer and Restart section. If the system input voltage falls below the UVLO threshold, or rises above the OVLO threshold, the GATE pin is pulled low by the 4.2-mA pulldown current to switch off Q₁.

9.4.3 Fault Timer and Restart

When the current limit or power limit threshold is reached during turn-on, or as a result of a fault condition, the gate-to-source voltage of Q₁ is modulated to regulate the load current and power dissipation in Q₁. When either limiting function is active, a 75-µA fault timer current source charges the external capacitor (C_T) at the TIMER pin as shown in Figure 22 (fault timeout period). If the fault condition subsides during the fault timeout period before the TIMER pin reaches 3.9 V, the LM5066 returns to the normal operating mode and C_T is discharged by the 1.5-mA current sink. If the TIMER pin reaches 3.9 V during the fault timeout period, Q₁ is switched off by a 4.2-mA pulldown current at the GATE pin. The subsequent restart procedure then depends on the selected retry configuration.

If the RETRY pin is high, the LM5066 latches the GATE pin low at the end of the fault timeout period. C_T is then discharged to ground by the 2.5-µA fault current sink. The GATE pin is held low by the 4.2-mA pulldown current until a power-up sequence is externally initiated by cycling the input voltage (V_IN), or momentarily pulling the UVLO/EN pin below its threshold with an open-collector or open-drain device as shown in Figure 23. The voltage at the TIMER pin must be <0.3 V for the restart procedure to be effective. The TIMER_LATCHED_OFF bit in the DIAGNOSTIC_WORD (E1h) register remains high while the latched off condition persists.

Figure 23. Latched Fault Restart Control

The LM5066 provides an automatic restart sequence which consists of the TIMER pin cycling between 3.9 and 1.2 V seven times after the fault timeout period, as shown in Figure 24. The period of each cycle is determined by the 75-µA charging current, the 2.5-µA discharge current, and the value of the capacitor, C_T. When the TIMER pin reaches 0.3 V during the eighth high-to-low ramp, the 20-µA current source at the GATE pin turns on Q₁. If the fault condition is still present, the fault timeout period and the restart sequence repeat. The RETRY pin allows selecting no retries or infinite retries. Finer control of the retry behavior can be achieved through the DEVICE_SETUP (D9h) register. Retry counts of 0, 1, 2, 4, 8, 16, or infinite may be selected by setting the appropriate bits in the DEVICE_SETUP (D9h) register.

Figure 24. Restart Sequence

9.4.4 Shutdown Control

The load current can be remotely switched off by taking the UVLO/EN pin below its threshold with an open collector or open-drain device, as shown in Figure 25. When UVLO/EN pin is released, the LM5066 switches on the FET with in-rush current and power limiting.

Figure 25. Shutdown Control

9.4.5 Enabling/Disabling and Resetting

The output can be disabled at during normal operation by either pulling the UVLO/EN pin to below its threshold or the OVLO pin above its threshold. This will cause the GATE voltage to be forced low with a pulldown strength of 4.2 mA. Toggling the UVLO/EN pin also resets the LM5066 from a latched-off state due to an overcurrent or over-power limit condition that caused the maximum allowed number of retries to be exceeded. While the UVLO/EN or OVLO pins can be used to disable the output, they have no effect on the volatile memory or address location of the LM5066. User-stored values for address, device operation, and warning and fault levels programmed through the SMBus are preserved while the LM5066 is powered regardless of the state of the UVLO/EN and OVLO pins. The output may also be enabled or disabled by writing 80h or 0h to the OPERATION (03h) register. To re-enable after a fault, the fault condition should be cleared by programing the OPERATION (03h) register with 0h and then 80h.

The SMBus address of the LM5066 is captured based-on the states of the ADR0, ADR1, and ADR2 pins (GND, NC, and VDD) during turn on and is latched into a volatile register after VDD has exceeded its POR threshold of 4.1 V. Reassigning or postponing the address capture is accomplished by holding the VREF pin to ground. Pulling the VREF pin low also resets the logic and erases the volatile memory of the LM5066. When released, the VREF pin charges up to its final value and the address is latched into a volatile register when the voltage at the VREF exceeds 2.55 V.

9.5.1 PMBus Command Support

The device features an SMBus interface that allows the use of PMBus commands to set warn levels, error masks, and get telemetry on V_IN, V_OUT, I_IN, V_AUX, and P_IN. The supported PMBus commands are shown in Table 2.

9.5.2 Standard PMBus Commands

9.5.3 Manufacturer Specific PMBus Commands

9.5.3.19 MFR_SPECIFIC_18: AVG_BLOCK_READ (E2h)

The AVG_BLOCK_READ command concatenates the DIAGNOSTIC_WORD with input and output average telemetry information (IIN, VOUT, VIN, and PIN) and temperature to capture all of the operating information of the part in a single PMBus transaction. The block is 12-bytes long with telemetry information sent out in the same manner as if an individual READ_AVG_XXX command had been issued (shown in Table 40). AVG_BLOCK_READ also specifies that the VIN, VOUT, and IIN measurements are all time-aligned whereas there is a chance they may not be if read with individual PMBus commands. To read data from the AVG_BLOCK_READ command, use the SMBus block read protocol.

Table 40. AVG_BLOCK_READ Register Format

Byte Count (Always 12)	(1 Byte)
DIAGNOSTIC_WORD	(1 word)
AVG_IIN	(1 word)
AVG_VOUT	(1 word)
AVG_VIN	(1 word)
AVG_PIN	(1 word)
TEMPERATURE	(1 word)

Figure 26. Command / Register and Alert Flow Diagram

9.5.4 Reading and Writing Telemetry Data and Warning Thresholds

All measured telemetry data and user-programmed warning thresholds are communicated in 12-bit two’s complement binary numbers read or written in 2-byte increments conforming to the direct format as described in section 8.3.3 of the PMBus Power System Management Protocol Specification 1.1 (Part II). The organization of the bits in the telemetry or warning word is shown in Table 41, where Bit_11 is the most significant bit (MSB) and Bit_0 is the least significant bit (LSB). The decimal equivalent of all warning and telemetry words are constrained to be within the range of 0 to 4095, with the exception of temperature. The decimal equivalent value of the temperature word ranges from 0 to 65535.

Conversion from direct format to real-world dimensions of current, voltage, power, and temperature is accomplished by determining appropriate coefficients as described in section 7.2.1 of the PMBus Power System Management Protocol Specification 1.1 (Part II). According to this specification, the host system converts the values received into a reading of volts, amperes, watts, or other units using the following relationship:

Equation 2.

where

• X = The calculated real-world value (volts, amps, watt, and so forth)
• m = The slope coefficient
• Y = A 2-byte two's complement integer received from device
• b = The offset, a 2-byte two's complement integer
• R = The exponent, a 1-byte two's complement integer

R is only necessary in systems where m is required to be an integer (for example, where m may be stored in a register in an integrated circuit). In those cases, R only needs to be large enough to yield the desired accuracy.

Take care to adjust the exponent coefficient, R, such that the value of m remains within the range of –32768 to 32767. For example, if a 5-mΩ sense resistor is used, the correct coefficients for the READ_IIN command with CL = VDD would be m = 5359, b = –120, R = –1.

9.5.5 Determining Telemetry Coefficients Empirically With Linear Fit

The coefficients for telemetry measurements and warning thresholds presented in Table 42 are adequate for the majority of applications. Current and power coefficients are dependent on R_SNS and must be calculated per application. Table 43 provides the equations necessary for calculating the current and power coefficients for the general case. These were obtained by characterizing multiple units over temperature and are considered optimal. The small signal nature of the current and power measurement makes it more susceptible to PCB parasitics than other telemetry channels. In addition there is some variation in R_SNS and the LM5066 itself. This may cause slight variations in the optimum coefficients (m, b, and R) for converting from digital values to real world values (for example, amps and watts). To maximize telemetry accuracy, the coefficients can be calibrated for a given board using empirical methods. This would determine optimum coefficients to cancel out the error from PCB parasitics, R_SNS variation, and the variation of LM5066. It is not considered good practice to take measurements on one board and use the computed coefficients for all units in production, because the R_SNS and the LM5066 on a given board are randomly chosen and do not represent a statistical mean. It is recommended to either calibrate all boards individually or to use the recommended coefficients from Table 43.

The optimal current coefficients for a given board can be determined using the following method:

1. While the LM5066 is in normal operation, measure the voltage across the sense resistor using Kelvin test points and a high accuracy DVM while controlling the load current. Record the integer value returned by the READ_AVG_IIN command (with the SAMPLES_FOR_AVG set to a value greater than 0) for two or more voltages across the sense resistor. For best results, the individual READ_AVG_IIN measurements should span nearly the full-scale range of the current (for example, voltage across R_SNS of 5 and 20 mV).
2. Convert the measured voltages to currents by dividing them by the value of R_SNS. For best accuracy, the value of R_SNS should be measured. Table 44 assumes a sense resistor value of 5 mΩ.

Table 44. Measurements for Linear Fit Determination of Current Coefficients

Measured Voltage Across RS (V)	Measured Current (A)	READ_AVG_IIN (Integer Value)
0.005	1	568
0.01	2	1108
0.02	4	2185

3. Using the spreadsheet (or a math program) determine the slope and the y-intercept of the data returned by the READ_AVG_IIN command versus the measured current. For the data shown in Table 42:
   • READ_AVG_IN value = slope × (Measured Current) + (y-intercept)
   • Slope = 538.9
   • Y-intercept = 29.5
4. To determine the m coefficient, simply shift the decimal point of the calculated slope to arrive at integer with a suitable number of significant digits for accuracy (typically 4) while staying with the range of –32768 to 32767. This shift in the decimal point equates to the R coefficient. For the slope value shown in the previous step, the decimal point would be shifted to the right once hence R = –1.
5. After the R coefficient has been determined, the b coefficient is found by multiplying the y-intercept by  10 ^–R. In this case the value of b = 295.
   • Calculated current coefficients:
   • m = 5389
   • b = 295
   • R = –1

Equation 3.

where

• X = The calculated real-world value (volts, amps, watts, temperature)
• m = The slope coefficient, is the 2-byte, two's complement integer
• Y = A 2-byte two's complement integer received from device
• b = The offset, a 2-byte two's complement integer
• R = The exponent, a 1-byte two's complement integer

This procedure can be repeated to determine the coefficients of any telemetry channel simply by substituting measured current for some other parameter (for example, power or voltage).

9.5.6 Writing Telemetry Data

There are several locations that require writing data if their optional usage is desired. Use the same coefficients previously calculated for your application, and apply them using this method as prescribed by the PMBus revision section 7.2.2 Sending a Value

Equation 4.

where

• X = The calculated real-world value (volts, amps, watts, temperature)
• m = The slope coefficient is the 2-byte, two's complement integer
• Y = A 2-byte two's complement integer received from device
• b = The offset, a 2-byte two's complement integer
• R = The exponent, a 1-byte two's complement integer

9.5.7 PMBus Address Lines (ADR0, ADR1, ADR2)

The three address lines are to be set high (connect to VDD), low (connect to GND), or open to select one of 27 addresses for communicating with the LM5066. Table 45 depicts 7-bit addresses (eighth bit is read/write bit).

9.5.8 SMBA Response

The SMBA effectively has two masks:

• The alert mask register at D8h
• The ARA automatic mask.

The ARA automatic mask is a mask that is set in response to a successful ARA read. An ARA read operation returns the PMBus address of the lowest addressed part on the bus that has its SMBA asserted. A successful ARA read means that this part was the one that returned its address. When a part responds to the ARA read, it releases the SMBA signal. When the last part on the bus that has an SMBA set has successfully reported its address, the SMBA signal de-asserts.

The way that the LM5066 releases the SMBA signal is by setting the ARA automatic mask bit for all fault conditions present at the time of the ARA read. All status registers will still the fault condition, but it does not generate a SMBA on that fault again until the ARA automatic mask is cleared by the host issuing a CLEAR_FAULTS command to this part. This should be done as a routine part of servicing an SMBA condition on a part, even if the ARA read is not done. Figure 27 depicts a schematic version of this flow.

Figure 27. Typical Flow Schematic for SMBA Fault