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ZHCSFJ8 September 2016 ISO5451-Q1

PRODUCTION DATA.

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請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。

機(jī)械數(shù)據(jù) (封裝 | 引腳)

DW|16

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購信息

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7 Specifications

7.1 Absolute Maximum Ratings⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

			MIN	MAX	UNIT
V_CC1	Supply voltage input side		GND1 - 0.3	6	V
V_CC2	Positive supply voltage output side	(V_CC2 – GND2)	–0.3	35	V
V_EE2	Negative supply voltage output side	(V_EE2 – GND2)	–17.5	0.3	V
V_(SUP2)	Total supply output voltage	(V_CC2 - V_EE2)	–0.3	35	V
V_OUT	Gate driver output voltage		V_EE2 - 0.3	V_CC2 + 0.3	V
I_(OUTH)	Gate driver high output current	Gate driver high output current (max pulse width = 10 μs, max duty cycle = 0.2%)		2.7	A
I_(OUTL)	Gate driver low output current			5.5	A
V_(LIP)	Voltage at IN+, IN-, FLT, RDY, RST		GND1 - 0.3	V_CC1 + 0.3	V
I_(LOP)	Output current of FLT, RDY			10	mA
V_(DESAT)	Voltage at DESAT		GND2 - 0.3	V_CC2 + 0.3	V
V_(CLAMP)	Clamp voltage		V_EE2 - 0.3	V_CC2 + 0.3	V
T_J	Junction temperature		–40	150	°C
T_STG	Storage temperature		-65	150	°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per AEC Q100-002⁽¹⁾	±4000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per AEC Q100-011	±1500	V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
V_CC1	Supply voltage input side	3		5.5	V
V_CC2	Positive supply voltage output side (V_CC2 – GND2)	15		30	V
V_EE2	Negative supply voltage output side (V_EE2 – GND2)	–15		0	V
V_(SUP2)	Total supply voltage output side (V_CC2 – V_EE2)	15		30	V
V_IH	High-level input voltage (IN+, IN-, RST)	0.7 x V_CC1		V_CC1	V
V_IL	Low-level input voltage (IN+, IN-, RST)	0		0.3 x V_CC1	V
t_UI	Pulse width at IN+, IN- for full output (C_LOAD = 1nF)	40			ns
t_RST	Pulse width at RST for resetting fault latch	800			ns
T_A	Ambient temperature	-40	25	125	°C

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		DW (SOIC)	UNIT
THERMAL METRIC⁽¹⁾		16 PINS	UNIT
R_θJA	Junction-to-ambient thermal resistance	99.6	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	48.5
R_θJB	Junction-to-board thermal resistance	56.5
ψ_JT	Junction-to-top characterization parameter	29.2
ψ_JB	Junction-to-board characterization parameter	56.5

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Power Rating

		VALUE	UNIT
P_D	Maximum power dissipation⁽¹⁾	1255	mW
P_ID	Maximum input power dissipation	175
P_OD	Maximum output power dissipation	1080

(1) Full chip power dissipation is de-rated 10.04 mW/°C beyond 25°C ambient temperature. At 125°C ambient temperature, a maximum of 251 mW total power dissipation is allowed. Power dissipation can be optimized depending on ambient temperature and board design, while ensuring that Junction temperature does not exceed 150°C.

7.6 Insulation Characteristics

PARAMETER		TEST CONDITIONS	SPECIFICATION	UNIT
CLR	External clearance⁽¹⁾	Shortest terminal-to-terminal distance through air	>8	mm
CPG	External creepage⁽¹⁾	Shortest terminal-to-terminal distance across the package surface	>8	mm
DTI	Distance through the insulation	Minimum internal gap (internal clearance)	>21	μm
CTI	Tracking resistance (comparative tracking index)	DIN EN 60112 (VDE 0303-11); IEC 60112;	>600	V
	Material Group	According to IEC 60664-1; UL 746A	I
	Overvoltage category (according to IEC 60664-1)	Rated Mains Voltage ≤ 300 V_RMS	I-IV
		Rated Mains Voltage ≤ 600 V_RMS	I-III
		Rated Mains Voltage ≤ 1000 V_RMS	I-II
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12⁽²⁾
V_IORM	Maximum repetitive peak isolation voltage	AC voltage (bipolar)	1420	V_PK
V_IOWM	Maximum isolation working voltage	AC voltage. Time dependent dielectric breakdown (TDDB) Test, see Figure 1	1000	V_RMS
V_IOWM	Maximum isolation working voltage	DC voltage	1420	V_DC
V_IOTM	Maximum Transient isolation voltage	V_TEST = V_IOTM, t = 60 sec (qualification), t = 1 sec (100% production)	8000	V_PK
V_IOSM	Maximum surge isolation voltage⁽³⁾	Test method per IEC 60065, 1.2/50 μs waveform, V_TEST = 1.6 x V_IOSM = 10000 V_PK (qualification)⁽³⁾	6250	V_PK
q_pd	Apparent charge⁽⁴⁾	Method a: After I/O safety test subgroup 2/3, V_ini = V_IOTM, t_ini= 60 s; V_pd(m) = 1.2 × V_IORM = 1704 V_PK , t_m = 10 s	≤5	pC
		Method a: After environmental tests subgroup 1, V_ini = V_IOTM, t_ini= 60 s; V_pd(m) = 1.6 × V_IORM = 2272 V_PK , t_m = 10 s	≤5
		Method b1: At routine test (100% production) and preconditioning (type test) V_ini = V_IOTM, t_ini= 60 s; V_pd(m) = 1.875× V_IORM = 2663 V_PK , t_m = 10 s	≤5
R_IO	Isolation resistance, input to output⁽⁵⁾	V_IO = 500 V, T_A = 25°C	> 10¹²	Ω
		V_IO = 500 V, 100°C ≤ T_A ≤ 125°C	> 10¹¹	Ω
		V_IO = 500 V at T_S = 150°C	> 10⁹	Ω
C_IO	Barrier capacitance, input to output⁽⁵⁾	V_IO = 0.4 x sin (2πft), f = 1 MHz	1	pF
	Pollution degree		2
UL 1577
V_ISO	Withstanding Isolation voltage	V_TEST = V_ISO, t = 60 sec (qualification), V_TEST = 1.2 × V_ISO = 6840 V_RMS, t = 1 sec (100% production)	5700	V_RMS

(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.

(2) This coupler is suitable for basic electrical insulation only within the maximum operating ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.

(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.

(4) Apparent charge is electrical discharge caused by a partial discharge (pd).

(5) All pins on each side of the barrier tied together creating a two-terminal device

7.7 Safety Limiting Values

Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures.

PARAMETER		TEST CONDITIONS	MAX	UNIT
I_S	Safety input, output or supply current	θ_JA = 99.6°C/W, V_I = 3.6 V, T_J = 150°C, T_A = 25°C	349	mA
		θ_JA = 99.6°C/W, V_I = 5.5 V, T_J = 150°C, T_A = 25°C	228
		θ_JA = 99.6°C/W, V_I = 15 V, T_J = 150°C, T_A = 25°C	84
		θ_JA = 99.6°C/W, V_I = 30 V, T_J = 150°C, T_A = 25°C	42
P_S	Safety input, output, or total power	θ_JA = 99.6°C/W, T_J = 150°C, T_A = 25°C	1255⁽¹⁾
T_S	Maximum ambient safety temperature		150	°C

(1) Input, output, or the sum of input and output power should not exceed this value

7.8 Safety-Related Certifications

over operating free-air temperature range (unless otherwise noted)

VDE	CSA	UL	CQC	TUV
Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 and DIN EN 60950-1 (VDE 0805 Teil 1):2011-01	Plan to certify under CSA Component Acceptance Notice 5A, IEC 60950-1 and IEC 60601-1	Certified according to UL 1577 Component Recognition Program	Certified according to GB 4943.1-2011	Certified according to EN 61010-1:2010 (3rd Ed) and EN 60950-1:2006/A11:2009/A1:2010/ A12:2011/A2:2013
Reinforced Insulation Maximum Transient isolation voltage, 8000 V_PK; Maximum surge isolation voltage, 6250 V_PK, Maximum repetitive peak isolation voltage, 1420 V_PK	Isolation Rating of 5700 V_RMS; Reinforced insulation per CSA 60950- 1- 07+A1+A2 and IEC 60950-1 (2nd Ed.), 800 V_RMS max working voltage (pollution degree 2, material group I) ; 2 MOPP (Means of Patient Protection) per CSA 60601-1:14 and IEC 60601-1 Ed. 3.1, 250 V_RMS (354 V_PK) max working voltage	Single Protection, 5700 V_RMS ⁽¹⁾	Reinforced Insulation, Altitude ≤ 5000m, Tropical climate, 400 V_RMSmaximum working voltage	5700 V_RMS Reinforced insulation per EN 61010-1:2010 (3rd Ed) up to working voltage of 600 V_RMS 5700 V_RMS Reinforced insulation per EN 60950-1:2006/A11:2009/A1:2010/ A12:2011/A2:2013 up to working voltage of 800 V_RMS
Certification completed Certificate number: 40040142	Certification planned	Certification completed File number: E181974	Certification completed Certificate number: CQC16001141761	Certification completed Client ID number: 77311

(1) Production tested ≥ 6840 V_RMS for 1 second in accordance with UL 1577.

The safety-limiting constraint is the absolute-maximum junction temperature specified in the Absolute Maximum Ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of a device installed in the High-K Test Board for Leaded Surface-Mount Packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance.

7.9 Electrical Characteristics

Over recommended operating conditions unless otherwise noted. All typical values are at T_A = 25°C, V_CC1 = 5 V,
V_CC2 – GND2 = 15 V, GND2 – V_EE2 = 8 V

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
VOLTAGE SUPPLY
V_IT+(UVLO1)	Positive-going UVLO1 threshold voltage input side (V_CC1 – GND1)				2.25	V
V_IT-(UVLO1)	Negative-going UVLO1 threshold voltage input side (V_CC1 – GND1)		1.7			V
V_HYS(UVLO1)	UVLO1 Hysteresis voltage (V_IT+ – V_IT–) input side			0.24		V
V_IT+(UVLO2)	Positive-going UVLO2 threshold voltage output side (V_CC2 – GND2)			12	13	V
V_IT-(UVLO2)	Negative-going UVLO2 threshold voltage output side (V_CC2 – GND2)		9.5	11		V
V_HYS(UVLO2)	UVLO2 Hysteresis voltage (V_IT+ – V_IT–) output side			1		V
I_Q1	Input supply quiescent current			2.8	4.5	mA
I_Q2	Output supply quiescent current			3.6	6	mA
LOGIC I/O
V_IT+(IN,RST)	Positive-going input threshold voltage (IN+, IN-, RST)				0.7 x V_CC1	V
V_IT-(IN,RST)	Negative-going input threshold voltage (IN+, IN-, RST)		0.3 x V_CC1			V
V_HYS(IN,RST)	Input hysteresis voltage (IN+, IN-, RST)			0.15 x V_CC1		V
I_IH	High-level input leakage at (IN+) ⁽¹⁾	IN+ = V_CC1		100		µA
I_IL	Low-level input leakage at (IN-, RST) ⁽²⁾	IN- = GND1, RST = GND1		-100		µA
I_PU	Pull-up current of FLT, RDY	V_(RDY) = GND1, V_(FLT) = GND1		100		µA
V_OL	Low-level output voltage at FLT, RDY	I_(FLT) = 5 mA			0.2	V
GATE DRIVER STAGE
V_(OUTPD)	Active output pull-down voltage	I_OUT = 200 mA, V_CC2 = open			2	V
V_(OUTH)	High-level output voltage	I_OUT = –20 mA	V_CC2 - 0.5	V_CC2 - 0.24		V
V_(OUTL)	Low-level output voltage	I_OUT = 20 mA		V_EE2 + 13	V_EE2 + 50	mV
I_(OUTH)	High-level output peak current	IN+ = high, IN- = low, V_OUT = V_CC2 - 15 V	1.5	2.5		A
I_(OUTL)	Low-level output peak current	IN+ = low, IN- = high, V_OUT = V_EE2 + 15 V	3.4	5		A
ACTIVE MILLER CLAMP
V_(CLP)	Low-level clamp voltage	I_(CLP) = 20 mA		V_EE2 + 0.015	V_EE2 + 0.08	V
I_(CLP)	Low-level clamp current	V_(CLAMP) = V_EE2 + 2.5 V	1.6	2.5		A
V_(CLTH)	Clamp threshold voltage		1.6	2.1	2.5	V
SHORT CIRCUIT CLAMPING
V_{(CLP_OUT)}	Clamping voltage (V_OUT - V_CC2)	IN+ = high, IN- = low, t_CLP=10 µs, I_(OUTH) = 500 mA		0.8	1.3	V
V_{(CLP_CLAMP)}	Clamping voltage (V_CLP - V_CC2)	IN+ = high, IN- = low, t_CLP=10 µs, I_(CLP) = 500 mA		1.3		V
V_{(CLP_CLAMP)}	Clamping voltage at CLAMP	IN+ = High, IN- = Low, I_(CLP) = 20 mA		0.7	1.1	V
DESAT PROTECTION
I_(CHG)	Blanking capacitor charge current	V_(DESAT) - GND2 = 2 V	0.42	0.5	0.58	mA
I_(DCHG)	Blanking capacitor discharge current	V_(DESAT) - GND2 = 6 V	9	14		mA
V_(DSTH)	DESAT threshold voltage with respect to GND2		8.3	9	9.5	V
V_(DSL)	DESAT voltage with respect to GND2, when OUT is driven low		0.4		1	V

(1) I_IH for IN-, RST pin is zero as they are pulled high internally.

(2) I_IL for IN+ is zero, as it is pulled low internally.

7.10 Switching Characteristics

Over recommended operating conditions unless otherwise noted. All typical values are at T_A = 25°C, V_CC1 = 5 V,
V_CC2 – GND2 = 15 V, GND2 – V_EE2 = 8 V

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_r	Output signal rise time	C_LOAD = 1 nF, see Figure 38, Figure 39 and Figure 40	12	20	35	ns
t_f	Output signal fall time		12	20	37	ns
t_PLH, t_PHL	Propagation Delay			76	110	ns
t_sk-p	Pulse Skew \|t_PHL – t_PLH\|				20	ns
t_sk-pp	Part-to-part skew				30⁽¹⁾	ns
t_GF	Glitch filter on IN+, IN-, RST		20	30	40	ns
t_{DESAT (10%)}	DESAT sense to 10% OUT delay		300	415	500	ns
t_{DESAT (GF)}	DESAT glitch filter delay			330		ns
t_{DESAT (FLT)}	DESAT sense to FLT-low delay	see Figure 40		2000	2420	ns
t_LEB	Leading edge blanking time	see Figure 38 and Figure 39	330	400	500	ns
t_GF(RSTFLT)	Glitch filter on RST for resetting FLT		300		800	ns
C_I	Input capacitance⁽²⁾	V_I = V_CC1/2 + 0.4 x sin (2πft), f = 1 MHz, V_CC1 = 5 V		2		pF
CMTI	Common-mode transient immunity	V_CM = 1500 V, see Figure 41	50	100		kV/μs

(1) Measured at same supply voltage and temperature condition

(2) Measured from input pin to ground.

7.11 Safety and Insulation Characteristics Curves

T_A upto 150°C

Stress-voltage frequency = 60 Hz

Figure 1. Reinforced High-Voltage Capacitor Life Time Projection

Figure 2. Thermal Derating Curve for Safety Limiting Current per VDE

Figure 3. Thermal Derating Curve for Safety Limiting Power per VDE

7.12 Typical Characteristics

V_CC2 = 30 V

Figure 4. Output High Drive Current vs Temperature

Figure 6. Output High Drive Current vs Output Voltage

Unipolar: V_CC2 - V_EE2 = V_CC2 - GND2

Figure 8. DESAT Threshold Voltage vs Temperature

V_CC2 = 30 V

Figure 5. Output Low Drive Current vs Temperature

Figure 7. Output Low Drive Current vs Output Voltage

C_L = 1 nF	R_G = 0 Ω
V_CC2 - V_EE2 = V_CC2 - GND2 = 20 V

Figure 9. Output Transient Waveform

C_L = 10 nF	R_G = 0 Ω
V_CC2 - V_EE2 = V_CC2 - GND2 = 20 V

Figure 11. Output Transient Waveform

C_L = 100 nF	R_G = 0 Ω
V_CC2 - V_EE2 = V_CC2 - GND2 = 20 V

Figure 13. Output Transient Waveform

C_L = 100 nF	R_G = 10 Ω
V_CC2 - V_EE2 = V_CC2 - GND2 = 20 V

Figure 15. Output Transient Waveform DESAT and FLT

IN+ = Low

IN- = Low

Figure 17. I_CC1 Supply Current vs Temperature

Figure 19. I_CC1 Supply Current vs. Input Frequency

R_G = 10 Ω, 20kHz

Figure 21. I_CC2 Supply Current vs Load Capacitance

C_L = 1nF

R_G = 0 Ω

V_CC2 = 15 V

Figure 23. V_CC2 Propagation Delay vs Temperature

R_G = 0 Ω

V_CC1 = 5 V

Figure 25. t_r Rise Time vs Load Capacitance

R_G = 10 Ω

V_CC1 = 5 V

Figure 27. t_r Rise Time vs Load Capacitance

Figure 29. Leading Edge Blanking Time With Temperature

C_L = 1 nF

Figure 31. DESAT Sense to FLT Low Delay vs Temperature

Figure 33. Miller Clamp Current vs Temperature

Figure 35. V_{CLP_CLAMP} - Short Circuit Clamp Voltage on Clamp Across Temperature

V_CC2 = 15 V

DESAT = 6 V

Figure 37. Blanking Capacitor Charging Current vs Temperature

C_L = 1 nF	R_G = 10 Ω
V_CC2 - V_EE2 = V_CC2 - GND2 = 20 V

Figure 10. Output Transient Waveform

C_L = 10 nF	R_G = 10 Ω
V_CC2 - V_EE2 = V_CC2 - GND2 = 20 V

Figure 12. Output Transient Waveform

C_L = 100 nF	R_G = 10 Ω
V_CC2 - V_EE2 = V_CC2 - GND2 = 20 V

Figure 14. Output Transient Waveform

IN+ = High

IN- = Low

Figure 16. I_CC1 Supply Current vs Temperature

Input Frequency = 1 kHz

Figure 18. I_CC2 Supply Current vs Temperature

No C_L

Figure 20. I_CC2 Supply Current vs Input Frequency

C_L = 1nF

R_G = 0 Ω

V_CC1 = 5 V

Figure 22. V_CC1 Propagation Delay vs Temperature

R_G = 10 Ω

V_CC1 = 5 V

Figure 24. Propagation Delay vs Load Capacitance

R_G = 0 Ω

V_CC1 = 5 V

Figure 26. t_f Fall Time v. Load Capacitance

R_G = 10 Ω

V_CC1 = 5 V

Figure 28. t_f Fall Time vs Load Capacitance

C_L = 10 nF

Figure 30. DESAT Sense to V_OUT 10% Delay vs Temperature

Figure 32. Reset to Fault Delay Across Temperature

Figure 34. Active Pull Down Voltage vs Temperature

Figure 36. V_{OUT_CLAMP} - Short Circuit Clamp Voltage on OUT Across Temperature

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購信息

7 Specifications

7.1 Absolute Maximum Ratings(1)

7.2 ESD Ratings

7.3 Recommended Operating Conditions

7.4 Thermal Information

7.5 Power Rating

7.6 Insulation Characteristics

7.7 Safety Limiting Values

7.8 Safety-Related Certifications

7.9 Electrical Characteristics

7.10 Switching Characteristics

7.11 Safety and Insulation Characteristics Curves

7.12 Typical Characteristics

7.1 Absolute Maximum Ratings⁽¹⁾