ZHCSI90E December 2017 – October 2019 ISO1042
PRODUCTION DATA.
請(qǐng)參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| DEVICE SWITCHING CHARACTERISTICS | ||||||
| tPROP(LOOP1) | Total loop delay, driver input TXD to receiver RXD, recessive to dominant | See Figure 20, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns; 1.71 V ≤ VCC1 ≤ 1.89 V | 70 | 125 | 198.0 | ns |
| See Figure 20, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns; 2.25 V ≤ VCC1 ≤ 5.5 V | 70 | 122 | 192.0 | ns | ||
| tPROP(LOOP2) | Total loop delay, driver input TXD to receiver RXD, dominant to recessive | See Figure 20, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns; 1.71 V ≤ VCC1 ≤ 1.89 V | 70 | 155 | 215.0 | ns |
| See Figure 20, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns; 2.25 V ≤ VCC1 ≤ 5.5 V | 70 | 152 | 215.0 | ns | ||
| tUV_RE_ENABLE | Re-enable time after Undervoltage event | Time for device to return to normal operation from VCC1 or VCC2 under voltage event | 300.0 | µs | ||
| CMTI | Common mode transient immunity | VCM = 1200 VPK, See Figure 24 | 85 | 100 | kV/µs | |
| DRIVER SWITCHING CHARACTERISTICS | ||||||
| tpHR | Propagation delay time, HIGH TXD to driver recessive | See Figure 17, RL = 60 Ω and CL = 100 pF; input rise/fall time (10% to 90%) on TXD =1 ns | 76 | 120 | ns | |
| tpLD | Propagation delay time, LOW TXD to driver dominant | 61 | 120 | |||
| tsk(p) | Pulse skew (|tpHR - tpLD|) | 14 | ||||
| tR | Differential output signal rise time | 45 | ||||
| tF | Differential output signal fall time | 45 | ||||
| VSYM | Output symmetry (dominant or recessive) (VO(CANH) + VO(CANL)) / VCC2 | See Figure 17 and Figure 31 , RTERM = 60 Ω, CSPLIT = 4.7 nF, CL = open, RL = open, TXD = 250 kHz, 1 MHz | 0.9 | 1.1 | V/V | |
| tTXD_DTO | Dominant time out | See Figure 22, RL = 60 Ω and CL = open | 1.2 | 3.8 | ms | |
| RECEIVER SWITCHING CHARACTERISTICS | ||||||
| tpRH | Propagation delay time, bus recessive input to RXD high output | See Figure 19, CL(RXD) = 15 pF | 75 | 130 | ns | |
| tpDL | Propogation delay time, bus dominant input to RXD low output | 63 | 130 | ns | ||
| tR | Output signal rise time(RXD) | 1.4 | ns | |||
| tF | Output signal fall time(RXD) | 1.8 | ns | |||
| FD TIMING PARAMETERS | ||||||
| tBIT(BUS) | Bit time on CAN bus output pins with tBIT(TXD) = 500 ns | See Figure 21, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns | 435.0 | 530.0 | ns | |
| Bit time on CAN bus output pins with tBIT(TXD) = 200 ns | See Figure 21, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns | 155.0 | 210.0 | ns | ||
| tBIT(RXD) | Bit time on RXD output pins with tBIT(TXD) = 500 ns | See Figure 21, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns | 400 | 550.0 | ns | |
| Bit time on RXD output pins with tBIT(TXD) = 200 ns | See Figure 21, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns | 120.0 | 220.0 | ns | ||
| ?tREC | Receiver timing symmetry with tBIT(TXD) = 500 ns | See Figure 21, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns; ΔtREC = tBIT(RXD) - tBIT(BUS) | -65.0 | 40.0 | ns | |
| Receiver timing symmetry with tBIT(TXD) = 200 ns | See Figure 21, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns; ΔtREC = tBIT(RXD) - tBIT(BUS) | -45.0 | 15.0 | ns | ||