ZHCSIN3A August 2018 – June 2019 DRV8350 , DRV8350R , DRV8353 , DRV8353R
PRODUCTION DATA.
Half-bridge overcurrent is also monitored by sensing the voltage drop across the external current-sense resistor with the SP pin. If at any time, the voltage on the SP input of the current-sense amplifier exceeds the VSEN_OCP threshold for longer than the tOCP_DEG deglitch time, a SEN_OCP event is recognized and action is done according to the OCP_MODE. On hardware interface devices, the VSENSE threshold is fixed at 1 V, tOCP_DEG is fixed at 4 µs, and the OCP_MODE for VSENSE is fixed for 8-ms automatic retry. On SPI devices, the VSENSE threshold is set through the SEN_LVL SPI register, the tOCP_DEG is set through the OCP_DEG SPI register, and the OCP_MODE bit can operate in four different modes: VSENSE latched shutdown, VSENSE automatic retry, VSENSE report only, and VSENSE disabled.
The VSENSE overcurrent protection operates in cycle-by-cycle (CBC) mode by default. This can be disabled on SPI device variants through the SPI registers. When in cycle-by-cycle (CBC) mode a new rising edge on the PWM inputs will clear an existing overcurrent fault.
Additionally, on SPI devices the OCP_ACT register setting can be set to change the SEN_OCP overcurrent response between linked and individual shutdown modes. When OCP_ACT is 0, a SEN_OCP fault will only effect the half-bridge in which it occurred. When OCP_ACT is 1, all three half-bridges will respond to a SEN_OCP fault on any of the other half-bridges. OCP_ACT defaults to 0, individual shutdown mode.