ZHCSIN3A August 2018 – June 2019 DRV8350 , DRV8350R , DRV8353 , DRV8353R
PRODUCTION DATA.
The driver control register is shown in Figure 57 and described in Table 14.
Register access type: Read/Write
| 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| OCP
_ACT |
DIS
_GDUV |
DIS
_GDF |
OTW
_REP |
PWM_MODE | 1PWM
_COM |
1PWM
_DIR |
COAST | BRAKE | CLR
_FLT |
|
| R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-00b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | |
| Bit | Field | Type | Default | Description |
|---|---|---|---|---|
| 10 | OCP_ACT | R/W | 0b |
0b = Associated half-bridge is shutdown in response to VDS_OCP and SEN_OCP 1b = All three half-bridges are shutdown in response to VDS_OCP and SEN_OCP |
| 9 | DIS_GDUV | R/W | 0b |
0b =VCP and VGLS undervoltage lockout fault is enabled 1b = VCP and VGLS undervoltage lockout fault is disabled |
| 8 | DIS_GDF | R/W | 0b |
0b = Gate drive fault is enabled 1b = Gate drive fault is disabled |
| 7 | OTW_REP | R/W | 0b |
0b = OTW is not reported on nFAULT or the FAULT bit 1b = OTW is reported on nFAULT and the FAULT bit |
| 6-5 | PWM_MODE | R/W | 00b |
00b = 6x PWM Mode 01b = 3x PWM mode 10b = 1x PWM mode 11b = Independent PWM mode |
| 4 | 1PWM_COM | R/W | 0b |
0b = 1x PWM mode uses synchronous rectification 1b = 1x PWM mode uses asynchronous rectification |
| 3 | 1PWM_DIR | R/W | 0b |
In 1x PWM mode this bit is ORed with the INHC (DIR) input |
| 2 | COAST | R/W | 0b |
Write a 1 to this bit to put all MOSFETs in the Hi-Z state |
| 1 | BRAKE | R/W | 0b |
Write a 1 to this bit to turn on all three low-side MOSFETs
|
| 0 | CLR_FLT | R/W | 0b |
Write a 1 to this bit to clear latched fault bits.
|