ZHCSP54 January 2022 DRV8316-Q1
PRODUCTION DATA
In the case of device latched faults, the DRV8316-Q1 family of devices goes to a partial shutdown state to help protect the power MOSFETs and system.
When the fault condition clears, the device can go to the operating state again by either setting the CLR_FLT SPI bit on SPI devices or issuing a reset pulse to the nSLEEP pin on either interface variant. The nSLEEP reset pulse (tRST) consists of a high-to-low-to-high transition on the nSLEEP pin. The low period of the sequence should fall with the tRST time window or else the device will start the complete shutdown sequence. The reset pulse has no effect on any of the regulators, device settings, or other functional blocks.