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ZHCSK74A August 2019 – April 2020 DRV425-Q1

PRODUCTION DATA.

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

RTJ|20
- MPQF156F

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購(gòu)信息

6.5 Electrical Characteristics

all minimum and maximum specifications are at T_A = 25°C, VDD = 3.0 V to 5.5 V, and I_DRV1 = I_DRV2 = 0 mA (unless otherwise noted); typical values are at VDD = 5.0 V.

PARAMETER			TEST CONDITIONS	MIN	TYP	MAX	UNIT
FLUXGATE SENSOR FRONT-END
	Offset		No magnetic field	–8	±2	8	µT
	Offset drift		No magnetic field		±5		nT/°C
G	Gain		Current at DRV1 and DRV2 outputs		12.2		mA/mT
	Gain error				±0.04%
	Gain drift		Best-fit line method		±7		ppm/°C
	Linearity error				0.1%
	Hysteresis		Magnetic field sweep from –10 mT to 10 mT		1.4		µT
	Noise		f = 0.1 Hz to 10 Hz		17		nTrms
	Noise density		f = 1 kHz		1.5		nT/√Hz
	Compensation range			–2		2	mT
	Saturation trip level for the ERROR pin⁽²⁾		Open-loop, uncompensated field		1.6		mT
	ERROR delay		Open-loop at B > 1.6 mT		4 to 6		µs
BW	Bandwidth		BSEL = 0, R_SHUNT = 22 Ω		32		kHz
BW	Bandwidth		BSEL = 1, R_SHUNT = 22 Ω		47		kHz
I_OS	Short-circuit current		VDD = 5 V		250		mA
I_OS	Short-circuit current		VDD = 3.3 V		150		mA
	Common-mode output voltage at the DRV1 and DRV2 pins				V_REFOUT		V
	Compensation coil resistance				100		Ω
SHUNT-SENSE AMPLIFIER
V_OO	Output offset voltage		V_AINP = V_AINN = V_REFIN, VDD = 3.0 V	–0.075	±0.01	0.075	mV
	Output offset voltage drift			–2	±0.4	2	µV/°C
CMRR	Common-mode rejection ratio, RTO⁽¹⁾		V_CM = –1 V to VDD + 1 V, V_REFIN = VDD / 2	–250	±50	250	µV/V
PSRR_AMP	Power-supply rejection ratio, RTO⁽¹⁾		VDD = 3.0 V to 5.5 V, V_CM = V_REFIN	–86	±4	86	µV/V
V_ICR	Common-mode input voltage range			–1		VDD + 1	V
z_id	Differential input impedance			16.5	20	23.5	kΩ
z_ic	Common-mode input impedance			40	50	60	kΩ
G_nom	Nominal gain		V_VOUT / (V_AINP – V_AINN)		4		V/V
E_G	Gain error			–0.3%	±0.02%	0.3%
	Gain error drift			–5	±1	5	ppm/°C
	Linearity error				12		ppm
	Voltage output swing from negative rail (OR pin trip level)⁽²⁾		VDD = 5.5 V, I_VOUT = 2.5 mA		48	85	mV
			VDD = 3.0 V, I_VOUT = 2.5 mA		56	100	mV
	Voltage output swing from positive rail (OR pin trip level)⁽²⁾		VDD = 5.5 V, I_VOUT = –2.5 mA	VDD – 85	VDD – 48		mV
			VDD = 3.0 V, I_VOUT = –2.5 mA	VDD – 100	VDD – 56		mV
	Signal overrange indication delay (OR pin)⁽²⁾		V_IN = 1-V step		2.5 to 3.5		µs
I_OS	Short-circuit current		VOUT connected to GND		–18		mA
I_OS	Short-circuit current		VOUT connected to VDD		20		mA
BW_–3dB	Bandwidth				2		MHz
SR	Slew rate				6.5		V/µs
t_sa	Settling time	Large signal	ΔV = ± 2 V to 1%, no external filter		0.9		µs
t_sa	Settling time	Small signal	ΔV = ± 0.4 V to 0.01%		8		µs
e_n	Output voltage noise density		f = 1 kHz, compensation loop disabled		170		nV/√Hz
V_REFIN	Input voltage range at pin REFIN		Input voltage range at REFIN pin	GND		VDD	V
VOLTAGE REFERENCE
V_REFOUT	Reference output voltage at the REFOUT pin		RSEL[1:0] = 00, no load	2.45	2.5	2.55	V
			RSEL[1:0] = 01, no load	1.6	1.65	1.7	V
			RSEL[1:0] = 1x, no load	45	50	55	% of VDD
	Reference output voltage drift		RSEL[1:0] = 0x	–50	±10	50	ppm/°C
	Voltage divider gain error drift		RSEL[1:0] = 1x	–50	±10	50	ppm/°C
PSRR_REF	Power-supply rejection ratio		RSEL[1:0] = 0x	–300	±15	300	µV/V
ΔV_O(ΔIO)	Load regulation		RSEL[1:0] = 0x, load to GND or VDD, ΔI_LOAD = 0 mA to 5 mA, T_A = –40°C to +125°C		0.15	0.35	mV/mA
ΔV_O(ΔIO)	Load regulation		RSEL[1:0] = 1x, load to GND or VDD, ΔI_LOAD = 0 mA to 5 mA, T_A = –40°C to +125°C		0.3	0.8	mV/mA
I_OS	Short-circuit current		REFOUT connected to VDD		20		mA
I_OS	Short-circuit current		REFOUT connected to GND		–18		mA
DIGITAL INPUTS/OUTPUTS (CMOS)
I_IL	Input leakage current				0.01		µA
V_IH	High-level input voltage		T_A = –40°C to +125°C	0.7 × VDD		VDD + 0.3	V
V_IL	Low-level input voltage		T_A = –40°C to +125°C	–0.3		0.3 × VDD	V
V_OH	High-level output voltage		Open-drain output	Set by external pullup resistor			V
V_OL	Low-level output voltage		4-mA sink current		0.3		V
POWER SUPPLY
I_Q	Quiescent current		I_DRV1/2 = 0 mA, 3.0 V ≤ VDD ≤ 3.6 V, T_A = –40°C to +125°C		6	8	mA
I_Q	Quiescent current		I_DRV1/2 = 0 mA, 4.5 V ≤ VDD ≤ 5.5 V, T_A = –40°C to +125°C		7	10	mA
V_POR	Power-on reset threshold				2.4		V

(1) Parameter value is referred-to-output (RTO).

(2) See the Magnetic Field Range, Overrange Indicator, and Error Flag section for details on the behavior of the ERROR and OR outputs.