ZHCSFB0D June 2016 – November 2023 DRV2510-Q1
PRODUCTION DATA
| MIN | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|
| ?(SCL) | Frequency at the SCL pin with no wait states | 400 | kHz | ||
| tw(H) | Pulse duration, SCL high | 0.6 | μs | ||
| tw(L) | Pulse duration, SCL low | 1.3 | μs | ||
| tsu(1) | Setup time, SDA to SCL | 100 | ns | ||
| th(1) | Hold time, SCL to SDA | 300 | ns | ||
| t(BUF) | Bus free time between stop and start condition | 1.3 | μs | ||
| tsu(2) | Setup time, SCL to start condition | 0.6 | μs | ||
| th(2) | Hold time, start condition to SCL | 0.6 | μs | ||
| tsu(3) | Setup time, SCL to stop condition | 0.6 | μs | ||
Figure 6-1 SCL and SDA Timing
Figure 6-2 Timing for Start and Stop Conditions