ZHCSR27D August 2020 – September 2022 BQ79612-Q1 , BQ79614-Q1 , BQ79616-Q1
PRODUCTION DATA
DEBUG_COML_VALID_HI
| Address | 0x0790 | |||||||
| Read Only | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
| Name | COUNT[7:0] | |||||||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| COUNT[7:0] = | The high-byte of COML frame counter to track the number of valid frames received or transmitted. Counter saturates when both DEBUG_COML_VALID_HI/LO is 0xFF. This register is latched and the related counter is reset when DEBUG_COML_DISCARD is read. | |||||||
DEBUG_COML_VALID_LO
| Address | 0x0791 | |||||||
| Read Only | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
| Name | COUNT[7:0] | |||||||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| COUNT[7:0] = | The low-byte of COML frame counter to track the number of valid frames received or transmitted. Counter saturates when both DEBUG_COML_VALID_HI/LO is 0xFF. This register is latched and the related counter is reset when DEBUG_COML_DISCARD is read. | |||||||