ZHCSHU6L march 2018 – august 2023 BQ77915
PRODUCTION DATA
- 1
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Revision History
- 5 說明（續(xù)）
- 6 Device Comparison Table
- 7 Pin Configuration and Functions
- 8 Specifications
-
9 Detailed Description
- 9.1 Overview
- 9.2 Functional Block Diagram
- 9.3
Feature Description
- 9.3.1 Protection Summary
- 9.3.2
Fault Operation
- 9.3.2.1 Operation in OV
- 9.3.2.2 Operation in UV
- 9.3.2.3 Operation in OW
- 9.3.2.4 Operation in OCD1
- 9.3.2.5 Operation in OCD2
- 9.3.2.6 Programming the OCD1/2 Delay Using the OCDP Pin
- 9.3.2.7 Operation in SCD
- 9.3.2.8 Operation in OCC
- 9.3.2.9 Overcurrent Recovery Timer
- 9.3.2.10 Load Detection and Load Removal Detection
- 9.3.2.11 Operation in OTC
- 9.3.2.12 Operation in OTD
- 9.3.2.13 Operation in UTC
- 9.3.2.14 Operation in UTD
- 9.3.3 Protection Response and Recovery Summary
- 9.3.4 Cell Balancing
- 9.3.5 HIBERNATE Mode Operation
- 9.3.6 Configuration CRC Check and Comparator Built-In-Self-Test
- 9.3.7 Fault Detection Method
- 9.3.8 State Comparator
- 9.3.9 DSG FET Driver Operation
- 9.3.10 CHG FET Driver Operation
- 9.3.11 External Override of CHG and DSG Drivers
- 9.3.12 Configuring 3-Series, 4-Series, or 5-Series Modes
- 9.3.13 Stacking Implementations
- 9.3.14 Zero-Volt Battery Charging Inhibition
- 9.4 Device Functional Modes
-
10Application and Implementation
- 10.1
Application Information
- 10.1.1 Recommended System Implementation
- 10.2 Typical Application
- 10.1
Application Information
- 11Power Supply Recommendations
- 12Layout
- 13Device and Documentation Support
- 14Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- PW|24
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
訂購(gòu)信息
9.3.12 Configuring 3-Series, 4-Series, or 5-Series Modes
The BQ77915 device supports 3-series, 4-series, or 5-series packs. To avoid accidentally detecting a UV fault on unused (shorted) cell inputs, the device must be configured for the specific cell count of the pack. This is set with the configuration pin, CCFG, which is mapped as shown in Table 9-7. The device periodically checks the CCFG status and takes tCCFG_DEG time to detect the pin status.
| CCFG | CONFIGURATION | CONNECT TO |
|---|---|---|
| < VCCFGL for tCCFG_DEG | 3 cells | VSS |
| Within VCCFGM for tCCFG_DEG | 4 cells | AVDD |
| > VCCFGH for tCCFG_DEG | 5 cells | Floating |
The CCFG pin should be tied to the recommended net from Table 9-7. The device compares the CCFG input voltage to the AVDD voltage and should never be set above the AVDD voltage. When the device configuration is for 5 series, leave the CCFG pin floating. The internal pin bias is approximately 33% of the AVDD voltage for 5-series configuration.
Figure 9-11 3-Series Configuration with Cell Balancing and HIBERNATE Mode Disabled
Figure 9-12 4-Series Configuration with Internal Cell Balancing and HIBERNATE Mode Enabled
Figure 9-13 5-Series Configuration with Internal Cell Balancing and HIBERNATE Mode Enabled