ZHCSDZ3D December 2014 – January 2017
PRODUCTION DATA.
| PIN | DESCRIPTION | ||
|---|---|---|---|
| NAME | NUMBER | I/O(1) | |
| BAT | 1 | P | Battery input pin. Primary power supply |
| PBI | 2 | P | Power supply backup input pin |
| VC4 | 3 | IA | Sense voltage input pin for the most positive cell, balance current input for the most positive cell, and battery stack measurement input |
| VC3 | 4 | IA | Sense voltage input pin for the third most positive cell, balance current input for the third most positive cell, and return balance current for the most positive cell |
| VC2 | 5 | IA | Sense voltage input pin for the second most positive cell, balance current input for the second most positive cell, and return balance current for the most positive cell |
| VC1 | 6 | IA | Sense voltage input pin for the least positive cell, balance current input for the least positive cell, and return balance current for the second most positive cell |
| SRN | 7 | IA | Analog input pin connected to the internal coulomb counter peripheral for integrating a small voltage between SRP and SRN, where SRP is the top of the sense resistor. |
| SRP | 8 | IA | Analog input pin connected to the internal coulomb counter peripheral for integrating a small voltage between SRP and SRN, where SRP is the top of the sense resistor. |
| VSS | 9 | P | Device ground |
| TS1 | 10 | IA | Thermistor input for temperature sensor channel 1 |
| TS2 | 11 | IA | Thermistor input for temperature sensor channel 2 |
| TS3 | 12 | IA | Thermistor input for temperature sensor channel 3 |
| TS4 | 13 | IA | Thermistor input for temperature sensor channel 4 |
| GPIO0 | 14 | I/O | Multi-function I/O (open drain). For more information, see IO Configuration in the bq40z60 Technical Reference Manual (SLUUA04). |
| GPIO1 | 15 | I/O | Multi-function I/O (open drain). See IO Configuration in the bq40z60 Technical Reference Manual (SLUUA04). |
| SMBD | 16 | I/OD | SMBus data pin |
| SMBC | 17 | I/OD | SMBus clock pin |
| VFB | 18 | IA | Feedback sense input for charger control loop |
| HSRN | 19 | IA | High sense resistor negative node input |
| HSRP | 20 | IA | High sense resistor positive node input |
| AFEFUSE | 21 | O | Fuse drive output pin |
| VCC | 22 | P | Power supply input |
| REGN | 23 | O | Charger FET gate drive regulator |
| PGND | 24 | P | Power ground |
| LODRV | 25 | O | Low side charging FET gate control output |
| PH | 26 | I/O | Charger phase signal input |
| HIDRV | 27 | O | High side charging FET gate control output |
| BTST | 28 | IA | High side bootstrap capacitor input |
| ACFET | 29 | O | AC FET gate control output |
| DSG | 30 | O | N-CH FET drive output pin |
| ACP | 31 | IA | Adapter input pin |
| CHG | 32 | O | N-CH FET drive output pin |