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ZHCSI54A September 2016 – May 2018 BQ25890H

PRODUCTION DATA.

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

RTW|24
- MPQF167C

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

RTW|24
- QFND125K

訂購(gòu)信息

7.5 Electrical Characteristics

V_{VBUS_UVLOZ}< V_VBUS< V_ACOV and V_VBUS> V_BAT + V_SLEEP, T_J = –40°C to +125°C and T_J = 25°C for typical values (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
QUIESCENT CURRENTS
I_BAT	Battery discharge current (BAT, SW, SYS) in buck mode	V_BAT = 4.2 V, V_(VBUS)< V_(UVLO), leakage between BAT and VBUS			5	µA
		High-Z mode, no VBUS, BATFET disabled (REG09[5]=1), battery monitor disabled, T_J< 85°C		12	23	µA
		High-Z mode, no VBUS, BATFET enabled (REG09[5]=0), battery monitor disabled, T_J< 85°C		32	60	µA
I_{(VBUS_HIZ)}	Input supply current (VBUS) in buck mode when High-Z mode is enabled	V_(VBUS)= 5 V, High-Z mode, no battery, battery monitor disabled		15	35	µA
I_{(VBUS_HIZ)}		V_(VBUS)= 12 V, High-Z mode, no battery, battery monitor disabled		25	50	µA
I_(VBUS)	Input supply current (V_BUS) in buck mode	V_BUS> V_(UVLO), V_BUS> V_BAT, converter not switching		1.5	3	mA
		V_BUS> V_(UVLO), V_BUS> V_BAT, converter switching, V_BAT = 3.2 V, I_SYS = 0A		3		mA
		V_BUS> V_(UVLO), V_BUS> V_BAT, converter switching, V_BAT = 3.8 V, I_SYS = 0 A		3		mA
I_(BOOST)	Battery discharge current in boost mode	V_BAT = 4.2 V, boost mode, I_(VBUS)= 0 A, converter switching, PFM_OTG_DIS=0		3		mA
I_(BOOST)	Battery discharge current in boost mode	V_BAT = 4.2 V, boost mode, I_(VBUS)= 0 A, converter switching, PFM_OTG_DIS=1		15		mA
VBUS/BAT POWER UP
V_{(VBUS_OP)}	VBUS operating range		3.9		14	V
V_{(VBUS_UVLOZ)}	VBUS for active I²C, no battery		3.6			V
V_(SLEEP)	Sleep mode falling threshold		25	65	120	mV
V_(SLEEPZ)	Sleep mode rising threshold		130	250	370	mV
V_(ACOV)	VBUS over-voltage rising threshold		14		14.6	V
V_(ACOV)	VBUS over-voltage falling threshold		13.5		14	V
V_BAT(UVLOZ)	Battery for active I2C, no VBUS		2.3			V
V_BAT(DPL)	Battery depletion falling threshold		2.15		2.5	V
V_BAT(DPLZ)	Battery depletion rising threshold		2.35		2.7	V
V_(VBUSMIN)	Bad adapter detection threshold			3.8		V
I_(BADSRC)	Bad adapter detection current source			30		mA
POWER-PATH MANAGEMENT
V_SYS	Typical system regulation voltage	I_(SYS) = 0 A, V_BAT> V_SYS(MIN), BATFET Disabled (REG09[5]=1)		V_BAT+ 50 mV		V
V_SYS	Typical system regulation voltage	I_(SYS) = 0 A, V_BAT< V_SYS(MIN), BATFET Disabled (REG09[5]=1)		V_SYS(MIN) + 150 mV		V
V_SYS(MIN)	Minimum DC system voltage output	V_BAT< V_SYS(MIN), SYS_MIN = 3.5 V (REG03[3:1]=101), I_SYS= 0 A	3.50	3.65		V
V_SYS(MAX)	Maximum DC system voltage output	V_BAT = 4.35 V, SYS_MIN = 3.5V (REG03[3:1]=101), I_SYS= 0 A		4.40	4.42	V
R_ON(RBFET)	Top reverse blocking MOSFET(RBFET) on-resistance between VBUS and PMID	T_J = –40°C to +85°C		27	38	mΩ
R_ON(RBFET)		T_J = –40°C to +125°C		27	44	mΩ
R_ON(HSFET)	Top switching MOSFET (HSFET) on-resistance between PMID and SW	T_J = –40°C to +85°C		27	39	mΩ
R_ON(HSFET)		T_J = –40°C to +125°C		27	47	mΩ
R_ON(LSFET)	Bottom switching MOSFET (LSFET) on-resistance between SW and GND	T_J = –40°C to +85°C		16	24	mΩ
R_ON(LSFET)		T_J = –40°C to +125°C		16	28	mΩ
V_(FWD)	BATFET forward voltage in supplement mode	BAT discharge current 10 mA		30		mV
V_BAT(GD)	Battery good comparator rising threshold	V_BAT rising	3.4	3.55	3.7	V
V_{BAT(GD_HYST)}	Battery good comparator falling threshold	V_BAT falling		100		mV
BATTERY CHARGER
V_{BAT(REG_RANGE)}	Typical charge voltage range		3.840		4.608	V
V_{BAT(REG_STEP)}	Typical charge voltage step			16		mV
V_BAT(REG)	Charge voltage resolution accuracy	V_BAT = 4.208 V (REG06[7:2]=010111) or V_BAT = 4.352 V (REG06[7:2]=100000) T_J = –40°C to +85°C	-0.5%		0.5%
I_{(CHG_REG_RANGE)}	Typical fast charge current regulation range		0		5056	mA
I_{(CHG_REG_STEP)}	Typical fast charge current regulation step			64		mA
I_{(CHG_REG_ACC)}	Fast charge current regulation accuracy	V_BAT = 3.1 V or 3.8 V, I_CHG = 128 mA T_J = –40°C to +85°C	-20%		20%
		V_BAT= 3.1 V or 3.8 V, I_CHG = 256 mA T_J = –40°C to +85°C	-10%		10%
		V_BAT= 3.1 V or 3.8 V, I_CHG=1792 mA T_J = –40°C to +85°C	-5%		5%
V_BAT(LOWV)	Battery LOWV falling threshold	Fast charge to precharge, BATLOWV (REG06[1]) = 1	2.6	2.8	2.9	V
V_BAT(LOWV)	Battery LOWV rising threshold	Precharge to fast charge, BATLOWV (REG06[1])=1 (Typical 200-mV hysteresis)	2.8	3	3.1	V
I_{(PRECHG_RANGE)}	Precharge current range		64		1024	mA
I_{(PRECHG_STEP)}	Typical precharge current step			64		mA
I_{(PRECHG_ACC)}	Precharge current accuracy	V_BAT=2.6 V, I_PRECHG = 256 mA	–10%		+10%
I_{(TERM_RANGE)}	Termination current range		64		1024	mA
I_{(TERM_STEP)}	Typical termination current step			64		mA
I_{(TERM_ACC)}	Termination current accuracy	I_TERM = 256 mA, I_CHG<= 1344 mA T_J = –20°C to +85°C	–12%		12%
I_{(TERM_ACC)}	Termination current accuracy	I_TERM = 256 mA, I_CHG> 1344 mA T_J = –20°C to +85°C	–20%		20%
V_(SHORT)	Battery short voltage	VBAT falling		2		V
V_{(SHORT_HYST)}	Battery short voltage hysteresis	VBAT rising		200		mV
I_(SHORT)	Battery short current	VBAT < 2.2 V		100		mA
V_(RECHG)	Recharge threshold below V_BATREG	V_BAT falling, VRECHG (REG06[0]=0) = 0		100		mV
V_(RECHG)	Recharge threshold below V_BATREG	V_BAT falling, VRECHG (REG06[0]=0) = 1		200		mV
I_SYS(LOAD)	System discharge load current	V_SYS = 4.2 V	30			mA
R_ON(BATFET)	SYS-BAT MOSFET (BATFET) on-resistance	T_J = 25°C		11	13	mΩ
R_ON(BATFET)	SYS-BAT MOSFET (BATFET) on-resistance	T_J = –40°C to +125°C		11	19	mΩ
INPUT VOLTAGE / CURRENT REGULATION
V_{IN(DPM_RANGE)}	Typical Input voltage regulation range		3.9		15.3	V
V_{IN(DPM_STEP)}	Typical Input voltage regulation step			100		mV
V_{IN(DPM_ACC)}	Input voltage regulation accuracy	VINDPM = 4.4 V, 9 V, T_J = –40°C to +105°C	3%		3%
I_{IN(DPM_RANGE)}	Typical Input current regulation range		100		3250	mA
I_{IN(DPM_STEP)}	Typical Input current regulation step			50		mA
I_{IN(DPM100_ACC)}	Input current 100-mA regulation accuracy V_BAT = 5 V, current pulled from SW	IINLIM (REG00[5:0]) =100 mA	85	90	100	mA
I_{IN(DPM_ACC)}	Input current regulation accuracy V_BAT = 5 V, current pulled from SW	USB150, IINLIM (REG00[5:0]) = 150 mA	125	135	150	mA
		USB500, IINLIM (REG00[5:0]) = 500 mA	440	470	500	mA
		USB900, IINLIM (REG00[5:0]) = 900 mA	750	825	900	mA
		Adapter 1.5 A, IINLIM (REG00[5:0]) = 1500 mA	1300	1400	1500	mA
I_IN(START)	Input current regulation during system start up	V_SYS = 2.2 V, IINLIM (REG00[5:0])> = 200 mA			200	mA
K_ILIM	I_INMAX = K_ILIM/R_ILIM	Input current regulation by ILIM pin = 1.5 A	315	350	385	A x Ω
D+/D- DETECTION
V_{(0P0_VSRC)}	D+/D– voltage source (0 V)	I(DP) < 1 mA; DP_DAC=001 or DM_DAC=001	-0.15	0	0.15	V
V_{(0P6_VSRC)}	D+/D– voltage source (0.6 V)	I(DP) < 1 mA; DP_DAC=010 or I(DM) < 1 m; ADM_DAC=010	0.5	0.6	0.7	V
V_{(1P2_VSRC)}	D+/D– voltage source (1.2 V)	I(DP) < 1 mA; DP_DAC=011 or I(DM) < 1 m; DM_DAC=011	1.075	1.2	1.325	V
V_{(2P0_VSRC)}	D+/D– voltage source (2.0 V)	I(DP) < 1 mA; DP_DAC=100 or I(DM) < 1 m; DM_DAC=100	1.875	2.0	2.125	V
V_{(2P7_VSRC)}	D+/D– voltage source (2.7 V)	I(DP) < 1 mA; DP_DAC=101 or I(DM) < 1 m; DM_DAC=101	2.575	2.7	2.825	V
V_{(3P3_VSRC)}	D+/D– voltage source (3.3 V)	I(DP) < 1 mA; DP_DAC=110 or I(DM) < 1 m; DM_DAC=110	3.15	3.3	3.45	V
V_{(3p45_VSRC)}	D+/D– voltage source (3.45 V)		3.3	3.45	3.6	V
I_{(10UA_ISRC)}	D+ connection check current source		7	10	14	µA
I_{(100UA_ISINK)}	D+/D– current sink (100 µA)		50	100	150	µA
I_{(DPDM_LKG)}	D+/D– leakage current	D–, switch open	–1		1	µA
I_{(DPDM_LKG)}	D+/D– leakage current	D+, switch open	–1		1	µA
I_{(1P6MA_ISINK)}	D+/D– current sink (1.6 mA)		1.45	1.60	1.75	µA
V_{(0P4_VTH)}	D+/D– low comparator threshold		250		400	mV
V_{(0P8_VTH)}	D+ low comparator threshold				0.8	V
V_{(2P7_VTH)}	D+/D– comparator threshold for non-standard adapter detection (divider 1, 3, or 4)		2.55		2.85	V
V_{(2P0_VTH)}	D+/D– comparator threshold for non-standard adapter detection (divider 1, 3)		1.85		2.15	V
V_{(1P2_VTH)}	D+/D– comparator threshold for non-standard adapter detection (divider 2)		1.05		1.35	V
R_{(D–_DWN)}	D– pulldown for connection check		14.25		24.8	kΩ
BAT OVER-VOLTAGE/CURRENT PROTECTION
V_BAT(OVP)	Battery over-voltage threshold	V_BAT rising, as percentage of V_BAT(REG)		104%
V_{BAT(OVP_HYST)}	Battery over-voltage hysteresis	V_BAT falling, as percentage of V_BAT(REG)		2%
I_{BAT(FET_OCP)}	System over-current threshold		9			A
THERMAL REGULATION AND THERMAL SHUTDOWN
T_REG	Junction temperature regulation accuracy	REG08[1:0] = 11		120		°C
T_SHUT	Thermal shutdown rising temperature	Temperature rising		160		°C
T_SHUT(HYS)	Thermal shutdown hysteresis	Temperature falling		30		°C
JEITA THERMISTOR COMPARATOR (BUCK MODE)
V_(T1)	T1 (0°C) threshold, charge suspended T1 below this temperature.	As percentage to V_(REGN)	72.75%	73.25%	73.75%
V_{(T1_HYS)}	Charge back to ICHG/2 (REG04[6:0]) and VREG (REG06[7:2]) above this temperature.	As percentage to V_(REGN)		1.4%
V_(T2)	T2 (10°C) threshold, charge back to ICHG/2 (REG04[6:0]) and VREG (REG06[7:2]) below this temperature.	As percentage to V_(REGN)	67.75%	68.25%	68.75%
V_{(T2_HYS)}	Charge back to ICHG (REG04[6:0]) and VREG (REG06[7:2]) above this temperature.	As percentage to V_(REGN)		1.4%
V_(T3)	T3 (45°C) threshold, charge back to ICHG (REG04[6:0]) and VREG-200 mV (REG06[7:2]) above this temperature.	As percentage to V_(REGN)	44.25v	44.75%	45.25%
V_{(T3_HYS)}	Charge back to ICHG (REG04[6:0]) and VREG (REG06[7:2]) below this temperature.	As percentage to V_(REGN)		1%
V_(T5)	T5 (60°C) threshold, charge suspended above this temperature.	As percentage to V_(REGN)	33.875%	34.375%	34.875%
V_{(T5_HYS)}	Charge back to ICHG (REG04[6:0]) and VREG-200 mV (REG06[7:2]) below this temperature.	As percentage to V_(REGN)		1.25%
COLD/HOT THERMISTOR COMPARATOR (BOOST MODE)
V_(BCOLD1)	Cold temperature threshold 1, TS pin voltage rising threshold	As percentage to V_REGN REG01[5] = 1 (Approximately –20°C w/ 103AT)	79.5%	80%	80.5%
V_{(BCOLD1_HYS)}	Cold temperature threshold 1, TS pin voltage falling threshold	As percentage to V_REGN REG01[5] = 1		1%
V_(BHOT2)	Hot temperature threshold 2, TS pin voltage falling threshold	As percentage to V_REGN REG01[7:6] = 10 (Approx. 65°C w/ 103AT)	30.75%	31.25%	31.75%
V_{(BHOT2_HYS)}	Hot temperature threshold 2, TS pin voltage rising threshold	As percentage to V_REGN REG01[7:6] =10		3%
PWM
F_SW	PWM switching frequency, and digital clock	Oscillator frequency	1.32		1.68	MHz
D_MAX	Maximum PWM duty cycle			97%
BOOST MODE OPERATION
V_{(OTG_REG_RANGE)}	Typical boost mode regulation voltage range		4.55		5.55	V
V_{(OTG_REG_STEP)}	Typical boost mode regulation voltage step			64		mV
V_{(OTG_REG_ACC)}	Boost mode regulation voltage accuracy	I(VBUS) = 0 A, BOOSTV=4.998V (REG0A[7:4] = 0111)	–3%		3%
V_{(OTG_BAT1)}	Minimum battery voltage to exit boost mode	BAT falling, MIN_VBAT_SEL=0	2.7		2.9	V
V_{(OTG_BAT2)}	Minimum battery voltage to exit boost mode	BAT falling, MIN_VBAT_SEL=1	2.4		2.6	V
V_{(OTG_BAT_EN)}	Minimum battery voltage to enter boost mode	BAT rising, MIN_VBAT_SEL=0	2.9		3.1	V
V_{(OTG_BAT_EN)}	Minimum battery voltage to enter boost mode	BAT rising, MIN_VBAT_SEL=1	2.7		2.9	V
I_(OTG)	Typical boost mode output current range		0.5		2.45	A
I_{(OTG_OCP_ACC)}	Boost mode RBFET over-current protection accuracy	BOOST_LIM =1.2 A (REG0A[2:0]=010)	1.2		1.65	A
V_{(OTG_OVP)}	Boost mode over-voltage threshold	Rising threshold	5.8	6		V
REGN LDO
V_(REGN)	REGN LDO output voltage	V_(VBUS) = 9 V, I_(REGN) = 40 mA	5.6	6	6.4	V
V_(REGN)	REGN LDO output voltage	V_(VBUS) = 5 V, I_(REGN) = 20 mA	4.7	4.8		V
I_(REGN)	REGN LDO current limit	V_(VBUS) = 9 V, V_(REGN) = 3.8 V	50			mA
ANALOG-TO-DIGITAL CONVERTER (ADC)
RES	Resolution	Rising threshold		7		bits
V_BAT(RANGE)	Typical battery voltage range	V_(VBUS)> V_BAT + V_(SLEEP) or OTG mode is enabled	2.304		4.848	V
V_BAT(RANGE)	Typical battery voltage range	V_(VBUS)< V_BAT + V_(SLEEP) and OTG mode is disabled	V_{SYS_MIN}		4.848	V
V_{(BAT_RES)}	Typical battery voltage resolution			20		mV
V_{(SYS_RANGE)}	Typical system voltage range	V_(VBUS)> V_BAT + V_(SLEEP) or OTG mode is enabled	2.304		4.848	V
V_{(SYS_RANGE)}	Typical system voltage range	V_(VBUS)< V_BAT + V_(SLEEP) and OTG mode is disabled	V_{SYS_MIN}		4.848	V
V_{(SYS_RES)}	Typical system voltage resolution			20		mV
V_{(VBUS_RANGE)}	Typical V_VBUS voltage range	V_(VBUS)> V_BAT + V_(SLEEP) or OTG mode is enabled	2.6		15.3	V
V_{(VBUS_RES)}	Typical V_VBUS voltage resolution			100		mV
I_BAT(RANGE)	Typical battery charge current range	V_(VBUS)> V_BAT + V_(SLEEP) and V_BAT> V_BAT(SHORT)	0		6.4	A
I_BAT(RES)	Typical battery charge current resolution			50		mA
V_{(TS_RANGE)}	Typical TS voltage range		21%		80%
V_{(TS_RES)}	Typical TS voltage resolution			0.47%
LOGIC I/O PIN (OTG, CE, QON)
V_IH	Input high threshold level		1.3
V_IL	Input low threshold level				0.4	V
I_IN(BIAS)	High Level Leakage Current	Pull-up rail 1.8 V			1	µA
V_(QON)	Internal /QON pull-up	Battery only mode		BAT		V
		V_(VBUS) = 9 V		5.8		V
		V_(VBUS) = 5 V		4.3		V
R_(QON)	Internal /QON pull-up resistance			200		kΩ
LOGIC I/O PIN (DSEL)
V_OL	Output low threshold level	I_OL = 2 mA, C_DSEL= 47 nF			0.4	V
V_OH	Output high threshold level	I_OH = 5 mA, C_DSEL= 47 nF, non-switching, I_(REGN) = 30 mA	4.5			V
LOGIC I/O PIN (INT, STAT)
V_OL	Output low threshold level	Sink current = 5 mA, sink current			0.4	V
I_{OUT_BIAS}	High level leakage current	Pull-up rail 1.8 V			1	µA
I²C INTERFACE (SCL, SDA)
V_IH	Input high threshold level, SCL and SDA	Pull-up rail 1.8 V	1.3
V_IL	Input low threshold level	Pull-up rail 1.8 V			0.4	V
V_OL	Output low threshold level	Sink current = 5 mA, sink current			0.4	V
I_BIAS	High level leakage current	Pull-up rail 1.8 V			1	µA