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ZHCSL85B May 2020 – April 2021 AMC3306M25

PRODUCTION DATA

封裝選項

機械數據 (封裝 | 引腳)

DWE|16
- MPSS091

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

6.9 Electrical Characteristics

all minimum and maximum specifications are at T_A = –40°C to +125°C, VDD = 3.0 V to 5.5 V, INP = –250 mV to +250 mV, INN = 0 V, and sinc³ filter with OSR = 256 (unless otherwise noted); typical values are at T_A = 25°C, CLKIN = 20 MHz, VDD = 3.3 V

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
ANALOG INPUT
R_IN	Single-ended input resistance	INN = HGND		19		kΩ
R_IND	Differential input resistance			22		kΩ
I_IB	Input bias current	INP = INN = HGND; I_IB = (I_IBP + I_IBN) / 2	–41	–30	–24	μA
I_IO	Input offset current⁽¹⁾	I_IO = I_IBP – I_IBN; INP = INN = HGND		±10		nA
C_IN	Single-ended input capacitance	INN = HGND, f_IN = 310 kHz		2		pF
C_IND	Differential input capacitance	f_IN = 310 kHz		1		pF
ACCURACY
E_O	Offset error⁽¹⁾	INN = INP = HGND, T_A = 25°C	–50	±10	50	μV
TCE_O	Offset error thermal drift⁽⁴⁾	INN = INP = HGND	–1		1	μV/°C
E_G	Gain error	T_A = 25°C	–0.2%	±0.005%	0.2%	%
TCE_G	Gain error drift⁽⁵⁾		–35		35	ppm/°C
DNL	Differential nonlinearity	Resolution: 16 bits	–0.99		0.99	LSB
INL	Integral nonlinearity	Resolution: 16 bits	–4	±1	4	LSB
SNR	Signal-to-noise ratio	f_IN = 1 kHz	81	83		dB
SINAD	Signal-to-noise + distortion	f_IN = 1 kHz	79	82.5		dB
THD	Total harmonic distortion⁽³⁾	5 MHz ≤ f_CLKIN ≤ 21 MHz, f_IN = 1 kHz		–96	–88	dB
SFDR	Spurious-free dynamic range	f_IN = 1 kHz	88	97		dB
CMRR	Common-mode rejection ratio	f_IN = 0 Hz, V_{CM min} ≤ V_IN ≤ V_{CM max}		–95		dB
CMRR	Common-mode rejection ratio	f_IN = 10 kHz, V_{CM min} ≤ V_IN ≤ V_{CM max}, V_INP = V_INN = 500 mV_PP		–84		dB
PSRR	Power-supply rejection ratio	VDD from 3.0 V to 5.5 V, at DC		–120		dB
PSRR	Power-supply rejection ratio	INP = INN = HGND, VDD from 3.0 V to 5.5 V, 10 kHz, 100 mV ripple		–120		dB
DIGITAL I/O
I_IN	Input leakage current	GND ≤ V_IN ≤ VDD	0		7	μA
C_IN	Input capacitance			4		pF
V_IH	High-level input voltage		0.7 × VDD		VDD + 0.3	V
V_IL	Low-level input voltage		–0.3		0.3 × VDD	V
C_LOAD	Output load capacitance			15	30	pF
V_OH	High-level output voltage	I_OH = –20 μA	VDD – 0.1			V
V_OH	High-level output voltage	I_OH = –4 mA	VDD – 0.4			V
V_OL	Low-level output voltage	I_OL = 20 μA			0.1	V
V_OL	Low-level output voltage	I_OL = 4 mA			0.4	V
CMTI	Common-mode transient immunity		75	135		kV/μs
POWER SUPPLY
IDD	Low-side supply current	no external load on HLDO		26	40	mA
IDD	Low-side supply current	1 mA external load on HLDO		28	42	mA
V_{DCDC_OUT}	DC/DC output voltage	DCDC_OUT to HGND	3.1	3.5	4.65	V
V_DCDCUV	DC/DC output undervoltage detection threshold voltage	V_{DCDC_OUT} falling	2.1	2.25		V
V_{HLDO_OUT}	High-side LDO output voltage	HLDO_OUT to HGND, up to 1 mA external load⁽²⁾	3	3.2	3.4	V
V_HLDOUV	High-side LDO output undervoltage detection threshold voltage	V_{HLDO_OUT} falling	2.4	2.6		V
I_H	High-side supply current for auxiliary circuitry	Load connected from HLDO_OUT to HGND; non-switching; –40℃ ≤ T_A ≤ 85℃⁽²⁾			1	mA
t_START	Device startup time	VDD step to 3.0 V to bitstream valid		0.9	1.4	ms

(1) The typical value includes one sigma statistical variation at nominal operating conditions.

(2) High-side LDO supports full external load (I_H) only up to T_A = 85℃. See the Isolated DC/DC Converter section for more details.

(3) THD is the ratio of the rms sum of the amplitues of first five higher harmonics to the amplitude of the fundamental.

(4) Offset error temperature drift is calculated using the box method, as described by the following equation:
TCE_O = (Value_MAX - Value_MIN) / TempRange

(5) Gain error temperature drift is calculated using the box method, as described by the following equation:
TCE_G (ppm) = (Value_MAX - Value_MIN) / (Value_(T=25℃) x TempRange) x 10⁶

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