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SBASAY8 October 2025 AMC0306M05

PRODMIX

請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。

7.4 Device Functional Modes

The AMC0x06M05 operates in one of the following states:

OFF-state: The low-side of the device (DVDD) is below the DVDD_UV threshold. The device is not responsive. DOUT is Hi-Z state. Internally, DOUT and CLKIN are clamped to DVDD and DGND by ESD protection diodes.
Missing high-side supply: The low-side of the device (DVDD) is supplied and within the limits listed in the Recommended Operating Conditions. The high-side supply (AVDD) is below the AVDD_UV threshold. The device outputs a constant bitstream of logic 0's, as described in the Output Behavior in Case of Missing High-Side Supply section.
Analog input overrange (positive full-scale input): AVDD and DVDD are within the recommended operating conditions. However, the analog input voltage V_IN = (V_INP– V_INN) is above the maximum clipping voltage (V_{Clipping, MAX}). The device outputs a logic 0 every 128 clock cycles, as described in the Output Behavior in Case of a Full-Scale Input section.
Analog input underrange (negative full-scale input): AVDD and DVDD are within the recommended operating conditions. However, the analog input voltage V_IN = (V_INP– V_INN) is below the minimum clipping voltage (V_{Clipping, MIN}). The device outputs a logic 1 every 128 clock cycles, as described in the Output Behavior in Case of a Full-Scale Input section.
Normal operation: AVDD, DVDD, and V_IN are within the recommended operating conditions. The device outputs a digital bitstream, as explained in the Digital Output section.

Table 7-1 lists the operational modes.

Table 7-1 Device Operational Modes

OPERATINAL MODE	AVDD	DVDD	V_IN	DEVICE RESPONSE
OFF	Don't care	V_DVDD < DVDD_UV	Don't care	DOUT is Hi-Z state. Internally, DOUT and CLKIN are clamped to DVDD and DGND by ESD protection diodes.
Missing high-side supply	V_AVDD < AVDD_UV	Valid⁽¹⁾	Don't care	The device outputs a constant bitstream of logic 0's, as described in the Output Behavior in Case of Missing High-Side Supply section.
Input overrange	Valid⁽¹⁾	Valid⁽¹⁾	V_IN > V_{Clipping, MAX}	The device outputs a logic 0 every 128 clock cycles, as described in the Output Behavior in Case of a Full-Scale Input section.
Input underrange	Valid⁽¹⁾	Valid⁽¹⁾	V_IN < V_{Clipping, MIN}	The device outputs a logic 1 every 128 clock cycles, as described in the Output Behavior in Case of a Full-Scale Input section.
Normal operation	Valid⁽¹⁾	Valid⁽¹⁾	Valid⁽¹⁾	Normal operation

(1) Valid denotes the value is within the recommended operating conditions.