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ZHCSPA8A March 2024 – August 2024 AFE7950-SP

PRODMIX

封裝選項

機械數(shù)據(jù) (封裝 | 引腳)

ALK|400
- MPBGAU3B

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

訂購信息

4.8 Digital Electrical Characteristics

Typical values at TA = +25°C, full temperature range is T_A,MIN = -40°C to T_J,MAX = +110°C (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
CML SerDes Inputs [8:1]SRX+/-
V_SRDIFF	SerDes Receiver Minimum Input Amplitude			100		mVpp
V_SRDIFF	SerDes Receiver Maximum Input Amplitude			1200		mVpp
V_SRCOM	SerDes Minimum Input Common Mode			0.5		V
V_SRCOM	SerDes Maximum Input Common Mode			0.6		V
Z_SRdiff	SerDes Internal Differential Termination⁽¹⁾			115		Ω
F_SerDes	SerDes Bit Rate	Minimum full rate mode		19		Gbps
F_SerDes	SerDes Bit Rate	Maximum full rate mode		24.75		Gbps
F_SerDes	SerDes Bit Rate	Minimum half rate mode		9.5		Gbps
F_SerDes	SerDes Bit Rate	Maximum half rate mode		16.25		Gbps
F_SerDes	SerDes Bit Rate	Minimum quarter rate mode		4.75		Gbps
F_SerDes	SerDes Bit Rate	Maximum quarter rate mode		8.125		Gbps
	Insertion Loss Tolerance⁽²⁾	Serdes supply = 1.8V		25		dB
TJ	Total Jitter Tolerance			0.42		UI
CML SerDes Outputs [8:1]STX+/-
V_STDIFF	SerDes Transmitter Minimum Output Amplitude	differential		500		mVpp
V_STDIFF	SerDes Transmitter Maximum Output Amplitude	differential		1000		mVpp
V_STCOM	SerDes Output Minimum Common Mode			0.5		V
V_STCOM	SerDes Output Common Mode			0.6		V
Z_STdiff	SerDes Output Impedance			115		Ω
TRF	Output rise and fall time	20-80%		8		ps
TEQS	Equalization range			7		dB
TTJ	Output total jitter			0.21		UI
CMOS I/O: GPIO{B/C/D/E}x, SPICLK, SPISDIO, SPISDO, SPISEN, RESETZ, BISTB0, BISTB1
V_IH	High-Level Input Voltage		0.6×VDD1P8GPIO			V
V_IL	Low-Level Input Voltage				0.4×VDD1P8GPIO	V
V_OH	High-Level Ouput Voltage		VDD1P8GPIO–0.2			V
V_OL	Low-Level Output Voltage				0.2	V
Differential Inputs: SYSREF+/- Mode A
F_SYSREFMAX	SYSREF Input Frequency Maximum			40		MHz
V_SWINGSRMAX	SYSREF Input Swing Maximum			1.8		Vppdiff⁽³⁾
V_SWINGSRMIN	SYSREF Input Swing Minimum	f_REF < 500MHz		0.3		Vppdiff⁽³⁾
V_SWINGSRMIN	SYSREF Input Swing Minimum	f_REF > 500MHz		0.6		Vppdiff⁽³⁾
V_COMSRMAX	SYSREF Input Common Mode Voltage Maximum			0.8		V
V_COMSRMIN	SYSREF Input Common Mode Voltage Minimum			0.6		V
Z_T	Input termination	differential		108 ⁽¹⁾		Ω
C_L	Input capacitance	Each pin to GND		0.5		pF
LVDS Inputs: 0SYNCIN+/- and 1SYNCIN+/-
V_ICOM	Input Common Voltage			1.2		V
V_ID	Differential Input Voltage swing			450		mVppdiff⁽³⁾
Z_T	Input termination	differential		100		Ω
LVDS Outputs: 0SYNCOUT+/- and 1SYNCOUT+/-
V_OCOM	Output Common Voltage			1.2		V
V_OD	Differential Output Voltage swing			355		mVppdiff⁽³⁾

(1) Default setting. SYSREF termination is programmable between nominally 100Ω, 150Ω and 300Ω

(2) Loss tolerance is bump to bump from STX to SRX

(3) Vppdiff is the difference between the maximum differential voltage (positive value) and minimum differential voltage (negative value).