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ZHCST39A December 2022 – September 2023 AFE11612-SEP

PRODUCTION DATA

封裝選項(xiàng)

6.6 Timing Characteristics

all minimum and maximum specifications at T_A = –55℃ to +125℃, all typical specifications at T_A = 25℃, AV_CC= 5.5 V, AV_DD = DV_DD = 4.5 V to 5.5 V, IOV_DD = 2.7 V to 5.5 V, internal reference, and DAC outputs unloaded (unless otherwise noted)

		MIN	MAX	UNIT
I²C STANDARD MODE TIMING REQUIREMENTS
f_(SCL)⁽¹⁾	I²C clock frequency	0	100	kHz
t_(LOW)	SCL clock low period	4.7		μs
t_(HIGH)	SCL clock high period	4.0		μs
t_(SUSTA)	Repeated start condition setup time	4.7		μs
t_(HDSTA)	Hold time after repeated start condition. After this period, the first clock is generated	4.0		μs
t_(SUSTO)	Stop condition setup time	4.0		μs
t_(BUF)	Bus free time between stop and start condition	4.7		μs
t_(SUDAT)	Data setup time	250		ns
t_(HDDAT)	Data hold time	0	3.45	μs
t_R,SCL	Clock rise time		1000	ns
t_F,SCL	Clock fall time		300	ns
t_R,SDA	Data rise time		1000	ns
t_F,SDA	Data fall time		300	ns
C_B	Capacitive load for each bus line		400	pF
I²C FAST MODE TIMING REQUIREMENTS
f_(SCL)⁽¹⁾	I²C clock frequency	0	400	kHz
t_(LOW)	SCL clock low period	1.3		μs
t_(HIGH)	SCL clock high period	0.6		μs
t_(SUSTA)	Repeated start condition setup time	0.6		μs
t_(HDSTA)	Hold time after repeated start condition. After this period, the first clock is generated	0.6		μs
t_(SUSTO)	Stop condition setup time	0.6		μs
t_(BUF)	Bus free time between stop and start condition	1.3		μs
t_(SUDAT)	Data setup time	100		ns
t_(HDDAT)	Data hold time	0	0.9	μs
t_R,SCL	Clock rise time	20 + 0.1 C_B	300	ns
t_F,SCL	Clock fall time	20 + 0.1 C_B	300	ns
t_R,SDA	Data rise time	20 + 0.1 C_B	300	ns
t_F,SDA	Data fall time	20 + 0.1 C_B	300	ns
C_B	Capacitive load for each bus line		400	pF
t_(SP)	Pulse duration of spike suppressed	0	50	ns
I²C Hs MODE TIMING REQUIREMENTS, C_B = 400 pF
f_(SCL)⁽¹⁾	I²C clock frequency	0	1.7	MHz
t_(LOW)	SCL clock low period	320		ns
t_(HIGH)	SCL clock high period	120		ns
t_(SUSTA)	Repeated start condition setup time	160		ns
t_(HDSTA)	Hold time after repeated start condition	160		ns
t_(SUSTO)	Stop condition setup time	160		ns
t_(SUDAT)	Data setup time	10		ns
t_(HDDAT)	Data hold time	0	150	ns
t_R,SCL	Clock rise time	20	80	ns
t_R,SCL1	Clock rise time after a repeated start condition and after an acknowledge bit	20	160	ns
t_F,SCL	Clock fall time	20	80	ns
t_R,SDA	Data rise time	20	160	ns
t_F,SDA	Data fall time	20	160	ns
C_B⁽²⁾	Capacitive load for each bus line		400	pF
t_(SP)	Pulse duration of spike suppressed	0	10	ns
I²C Hs MODE TIMING REQUIREMENTS, C_B = 10 pF to 100 pF
f_(SCL)	I²C clock frequency	0	3.4	MHz
t_(LOW)	SCL clock low period	160		ns
t_(HIGH)	SCL clock high period	60		ns
t_(SUSTA)	Repeated start condition setup time	160		ns
t_(HDSTA)	Hold time after repeated start condition	160		ns
t_(SUSTO)	Stop condition setup time	160		ns
t_(SUDAT)	Data setup time	10		ns
t_(HDDAT)	Data hold time	0	70	ns
t_R,SCL	Clock rise time	10	40	ns
t_R,SCL1	Clock rise time after a repeated start condition and after an acknowledge bit	10	80	ns
t_F,SCL	Clock fall time	10	40	ns
t_R,SDA	Data rise time	10	80	ns
t_F,SDA	Data fall time	10	80	ns
C_B⁽²⁾	Capacitive load for each bus line	10	100	pF
t_(SP)	Pulse duration of spike suppressed	0	10	ns
SPI TIMING REQUIREMENTS
f_(SCLK)	SCLK frequency		20	MHz
t_(SCLKHIGH)	SCLK high time	8		ns
t_(SCLKLOW)	SCLK low time	8		ns
t_(SDISU)	SDI setup time	5		ns
t_(SDIHD)	SDI hold time	4		ns
t_(SDODLY)⁽³⁾	SDO output delay	3	20	ns
t_(CSSU)	CS setup time	5		ns
t_(CSHD)	CS hold time	10		ns
t_(CSHIGH)	CS high time	30		ns

(1) Use an SCL operating frequency of at least 1 kHz to avoid the I²C timeout function.

(2) For bus line loads where CB is between 100 pF and 400 pF, linearly interpolate the timing parameters.

(3) SDO loaded with 10-pF load capacitance.

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購信息

6.6 Timing Characteristics