ZHCST39A December 2022 – September 2023 AFE11612-SEP
PRODUCTION DATA
The controller initiates the data transfer by generating a start condition. The start condition is when a high-to-low transition occurs on the SDA line while SCL is high. All I2C-compatible devices must recognize a start condition.
The controller then generates the SCL pulses, and transmits the 7-bit address and the read or write direction bit (R/W) on the SDA line. During all transmissions, the controller makes sure that data are valid. A valid data condition requires that the SDA line is stable during the entire high period of the clock pulse. All devices recognize the address sent by the controller and compare the address to the internal fixed addresses. Only the target device with a matching address generates an acknowledge by pulling the SDA line low during the entire high period of the ninth SCL cycle. When this acknowledge is detected, the controller recognizes that a communication link is established with a target.
The controller generates further SCL cycles to either transmit data to the target (R/W bit is 1) or receive data from the target (R/W bit is 0). In either case, the receiver must acknowledge the data sent by the transmitter. Therefore, an acknowledge signal can either be generated by the controller or by the target, depending on which one is the receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as necessary.
To signal the end of the data transfer, the controller generates a stop condition by pulling the SDA line from low-to-high while the SCL line is high. This action releases the bus and stops the communication link with the addressed target. All I2C-compatible devices must recognize the stop condition. When a stop condition is received, all devices recognize that the bus is released and wait for a start condition followed by a matching address.