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ZHCSM31B September 2020 – March 2022 ADC3660

PRODUCTION DATA

封裝選項

機械數(shù)據(jù) (封裝 | 引腳)

RSB|40
- MPQF185C

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

RSB|40
- QFND255H

訂購信息

6.6 Electrical Characteristics - DC Specifications

Typical values are over the operating free-air temperature range, at T_A = 25°C, full temperature range is T_MIN = –40°C to T_MAX = 105°C, ADC sampling rate = 65 MSPS, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, external 1.6 V reference, and –1-dBFS differential input, unless otherwise noted

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
DC ACCURACY
No missing codes			16			bits
PSRR		F_IN = 1 MHz		50		dB
DNL	Differential nonlinearity	F_IN = 5 MHz	-0.5	± 0.2	+1	LSB
INL⁽¹⁾	Integral nonlinearity	F_IN = 5 MHz	-4.5	± 2	+4.5	LSB
V_{OS_ERR}	Offset error		-130	2	130	LSB
V_{OS_DRIFT}	Offset drift over temperature			-3.5		LSB/oC
GAIN_ERR	Gain error	External 1.6V Reference		0		%FSR
GAIN_DRIFT	Gain drift over temperature	External 1.6V Reference		10.3		ppm/oC
GAIN_ERR	Gain error	Internal Reference		2.4		%FSR
GAIN_DRIFT	Gain drift over temperature	Internal Reference		108.8		ppm/oC
Transition Noise				1.5		LSB
ADC ANALOG INPUT (AINP/M, BINP/M)
FS	Input full scale	Differential		3.2		Vpp
V_CM	Input common model voltage		0.9	0.95	1.0	V
R_IN	Differential input resistance	F_IN = 100 kHz		8		kΩ
C_IN	Differential input Capacitance	F_IN = 100 kHz		7		pF
V_OCM	Output common mode voltage			0.95		V
BW	Analog Input Bandwidth (-3dB)			900		MHz
INTERNAL VOLTAGE REFERENCE
V_REF	Internal reference voltage			1.6		V
V_REFOutput Impedance				8		Ω
REFERENCE INPUT BUFFER (REFBUF)
External reference voltage				1.2		V
EXTERNAL VOLTAGE REFERENCE (VREF)
V_REF	External voltage reference			1.6		V
Input Current				0.3		mA
Input impedance				5.3		kΩ
CLOCK INPUT (CLKP/M)
Input clock frequency			0.5		65	MHz
V_ID	Differential input voltage			1	3.6	Vpp
V_CM	Input common mode voltage			0.9		V
R_IN	Single ended input resistance to common mode.			5		kΩ
C_IN	Single ended input capacitance			1.5		pF
Clock duty cycle			40	50	60	%
DIGITAL INPUTS (RESET, PDN, SCLK, SEN, SDIO)
V_IH	High level input voltage		1.4			V
V_IL	Low level input voltage				0.4	V
I_IH	High level input current			90	150	uA
I_IL	Low level input current		-150	-90		uA
C_I	Input capacitance			1.5		pF
DIGITAL OUTPUT (SDOUT)
V_OH	High level output voltage	I_LOAD = -400 uA	IOVDD – 0.1	IOVDD		V
V_OL	Low level output voltage	I_LOAD = 400 uA			0.1	V
DIGITAL SCMOS OUTPUTS (DA5/6, DB5/6)
Output data rate		per CMOS output pin			250	MHz
V_OH	High level output voltage	per CMOS output pin	IOVDD – 0.1	IOVDD		V
V_OL	Low level output voltage	I_LOAD = 400 uA			0.1	V
V_IH	High level input voltage	DCLKIN	IOVDD – 0.1	IOVDD		V
V_IL	Low level input voltage	DCLKIN			0.1	V

(1) Performance data shown is prior to decimation filtering. With DDC enabled, performance improves by the decimation filtering process.