ZHCSQQ1B june 2022 – august 2023 ADC32RF54 , ADC32RF55
PRODUCTION DATA
The decimation filter is configured with these register writes.
| ADDR | DATA | DESCRIPTION |
|---|---|---|
| 0x05 | 0x02 | Select DIGITAL page |
| 0x2C | Select single/dual/quad band | |
| 0x2D | Select decimation | |
| 0x05 | 0x04 | Select JESD page |
| 0x22 | Select LMFS mode | |
| 0x24 | Select DDC CLK setting | |
| 0x25 | Select JESD TX CLK DIV setting | |
| 0x9F | Select JESD PLL1/2 settings | |
| 0xA0 | Select JESD PLL INPUT1 setting | |
| 0xA1 | Select JESD PLL INPUT2 settings | |
| 0xA2 | Select JESD PLL INPUT3 settings |