ZHCSEU3E July 2014 – June 2022 ADC3221 , ADC3222 , ADC3223 , ADC3224
PRODUCTION DATA
| MIN | NOM | MAX | UNIT | |||
|---|---|---|---|---|---|---|
| SUPPLIES | ||||||
| AVDD | Analog supply voltage range | 1.7 | 1.8 | 1.9 | V | |
| DVDD | Digital supply voltage range | 1.7 | 1.8 | 1.9 | V | |
| ANALOG INPUT | ||||||
| VID | Differential input voltage | For input frequencies < 450 MHz | 2 | VPP | ||
| For input frequencies < 600 MHz | 1 | |||||
| VIC | Input common-mode voltage | VCM ± 0.025 | V | |||
| CLOCK INPUT | ||||||
| Input clock frequency | Sampling clock frequency | 15(3) | 125(1) | MSPS | ||
| Input clock amplitude (differential) | Sine wave, ac-coupled | 0.2 | 1.5 | VPP | ||
| LVPECL, ac-coupled | 1.6 | |||||
| LVDS, ac-coupled | 0.7 | |||||
| Input clock duty cycle | 35% | 50% | 65% | |||
| Input clock common-mode voltage | 0.95 | V | ||||
| DIGITAL OUTPUTS | ||||||
| CLOAD | Maximum external load capacitance from each output pin to GND | 3.3 | pF | |||
| RLOAD | Differential load resistance placed externally | 100 | Ω | |||