ZHCSP07A October 2021 – October 2024 ADC12DJ800 , ADC12QJ800 , ADC12SJ800
PRODUCTION DATA
The 64B/66B link layer does not use an initial lane alignment sequence (ILAS) like the 8B/10B link layer. Therefore, the receiver must use a different scheme to align lanes using the elastic buffer. In 8B/10B mode, the ILAS triggers the elastic buffer to start buffering the data for each lane. After all lanes have started buffering the data, the elastic buffers for each lane are released at a release point determined by the release buffer delay (RBD) parameter and the phase of the LMFC. In 64B/66B mode, the process starts by having all lanes achieve block, multiblock and extended multiblock alignment. Once all lanes have achieved alignment, the receiver can begin buffering data in the elastic buffers at the start of the next extended multiblock on each lane. The data is released at the next release point after all lanes have seen the start of an extended multiblock and have started buffering the data. The release point is defined relative to the LEMC edge and the programmed RBD value, the most intuitive of which is to release on the LEMC edge itself. The release point must be chosen to avoid the region of the LEMC containing variation in the data delay on each lane from startup to startup.