ZHCSI83C may 2018 – may 2023 ADC12DL3200
PRODUCTION DATA
Figure 8-14 to Figure 8-16 provide examples of the critical traces routed on the device evaluation module (EVM). Figure 8-17 provides an example printed circuit board (PCB) layer stackup.
Figure 8-14 Top Layer Routing: Analog Inputs, CLK and SYSREF, DA0-3, DB0-3
Figure 8-15 GND1 Cutouts to Optimize Impedance of Component Pads
Figure 8-16 Bottom Layer Routing: Additional CLK Routing, DA4-7, DB4-7
Figure 8-17 Example PCB Stackup