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ZHCSI83C may 2018 – may 2023 ADC12DL3200

PRODUCTION DATA

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

ACF|256
- MPBGAO1C
ALJ|256
- MPBGAS8B

散熱焊盤(pán)機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購(gòu)信息

6.5 Electrical Characteristics: DC Specifications

typical values at T_A = +25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000), f_IN = 248 MHz, A_IN = –1 dBFS, f_CLK = maximum rated clock frequency, filtered 1-V_PP-DIFF sine-wave clock, DES_EN = 1, LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over operating free-air temperature range provided in the Recommended Operating Conditions table

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
DC ACCURACY
	Resolution	Resolution with no missing codes		12		Bits
DNL	Differential nonlinearity	Maximum positive excursion from ideal step size		0.3		LSB
DNL	Differential nonlinearity	Maximum negative excursion from ideal step size		–0.3		LSB
INL	Integral nonlinearity	Maximum positive excursion from ideal transfer function		1.6		LSB
INL	Integral nonlinearity	Maximum negative excursion from ideal transfer function		–2.0		LSB
ANALOG INPUTS (INA±, INB±)
V_OFF	Offset Error	CAL_OS = 0		±2.0		mV
V_OFF	Offset Error	CAL_OS = 1		±0.3		mV
V_{OFF_ADJ}	Input offset voltage adjustment range	Available offset correction range (see CAL_OS bit in the CAL_CFGO register or the OADJ_A_FG0_VINA register)		±55		mV
V_{OFF_ DRIFT}	Offset drift	Foreground calibration at nominal temperature only		14		μV/°C
V_{OFF_ DRIFT}	Offset drift	Foreground calibration at each temperature		4		μV/°C
V_{IN_FSR}	Analog differential input full-scale range	Default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000)	750	800	850	mV_PP
		Maximum full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xFFFF)	1000	1040
		Minimum full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0x2000)		480	525
V_{IN_FSR_DRIFT}	Analog differential input full-scale range drift	Default FS_RANGE_A and FS_RANGE_B setting, foreground calibration at nominal temperature only, inputs driven by 50-Ω source, includes effect of R_IN drift		0.037		%/°C
V_{IN_FSR_DRIFT}	Analog differential input full-scale range drift	Default FS_RANGE_A and FS_RANGE_B setting, foreground calibration at each temperature, inputs driven by 50-Ω source, includes effect of R_IN drift		0.006		%/°C
V_{IN_FSR_MATCH}	Analog differential input full-scale range matching	Matching between INA± and INB±, default setting, dual channel mode		0.53%
R_IN	Single-ended input resistance to AGND	Each input terminal is terminated to AGND, measured at T_A = 25°C	48	50	52	Ω
R_{IN_ TEMPCO}	Input termination linear temperature coefficient			13.7		mΩ/°C
C_IN	Single-ended input capacitance	Single-channel mode measured at DC		0.45		pF
C_IN	Single-ended input capacitance	Dual-channel mode measured at DC		0.45		pF
TEMPERATURE DIODE CHARACTERISTICS (TDIODE±)
ΔV_BE	Temperature diode voltage slope	Forced forward current of 100 μA. Offset voltage (approximately 0.792 V at 0°C) varies with process and must be measured for each part. Perform offset measurements with the device unpowered or with the PD pin asserted to minimize device self-heating.		-1.33		mV/°C
BANDGAP VOLTAGE OUTPUT (BG)
V_BG	Reference output voltage	I_L ≤ 100 μA		1.1		V
V_{BG_ DRIFT}	Reference output temperature drift	I_L ≤ 100 μA		–85		μV/°C
CLOCK INPUTS (CLK±, SYSREF±, TMSTP±)
Z_T	Internal termination	Differential termination with DEVCLK_LVPECL_EN = 0, SYSREF_LVPECL_EN = 0 and TMSTP_LVPECL_EN = 0		100		Ω
Z_T	Internal termination	Single ended termination to GND (per pin) with DEVCLK_LVPECL_EN = 0, SYSREF_LVPECL_EN = 0 and TMSTP_LVPECL_EN = 0		50		Ω
V_CM	Input common-mode voltage, self-biased	Self-biasing common-mode voltage for CLK± when AC coupled (DEVCLK_LVPECL_EN must be set to 0)		0.3		V
		Self-biasing common-mode voltage for SYSREF± when AC coupled (SYSREF_LVPECL_EN must be set to 0) and with receiver enabled (SYSREF_RECV_EN = 1).		0.3
		Self-biasing common-mode voltage for SYSREF± when AC coupled (SYSREF_LVPECL_EN must be set to 0) and with receiver disabled (SYSREF_RECV_EN = 0).		VA11
C_{L_DIFF}	Differential input capacitance	Between positive and negative differential input pins		0.1		pF
C_{L_SE}	Single-ended input capacitance	Each input to ground		0.5		pF
LVDS OUTPUTS (DACLK±, DASTR±, DA[11:0]±, DBCLK±, DBSTR±, DB[11:0]±, DCCLK±, DCSTR±, DC[11:0]±, DDCLK±, DDSTR±, DD[11:0]±)
V_DIFF	Differential output peak-to-peak voltage, DC measurement	Default swing (HSM), 100-Ω load	400	720	900	mV_PP-DIFF
		Low swing (LSM), 100-Ω load		350
		Low swing high-Z mode (HZM), high-impedance load		380
V_CM	Output common-mode voltage, tracks with VLVDS	VLVDS = 1.9 V		1.3		V
V_CM	Output common-mode voltage, tracks with VLVDS	VLVDS = 1.1 V		0.5		V
I_{OS_DIFF}	Differential short-circuit current	Positive and negative outputs shorted together		5		mA
I_{OS_GND}	Short-circuit current to ground	Either positive or negative output tied to ground		20		mA
Z_DIFF	Differential output impedance	Measured at DC		300		Ω
CMOS INTERFACE: SCLK, SDI, SDO, SCS, PD, CALSTAT, CALTRIG, ORA0, ORA1, ORB0, ORB1, SYNCSE
I_IH	High-level input current				40	μA
I_IL	Low-level input current		–40			μA
C_I	Input capacitance			2		pF
V_OH	High-level output voltage	I_LOAD = –400 μA	1.65			V
V_OL	Low-level output voltage	I_LOAD = 400 μA			150	mV