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ZHCSI83C may 2018 – may 2023 ADC12DL3200

PRODUCTION DATA

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

ACF|256
- MPBGAO1C
ALJ|256
- MPBGAS8B

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購(gòu)信息

7.3.4 Clocking

The clocking subsystem of the ADC12DL3200 has two input signals: the device clock (CLK+, CLK–) and SYSREF (SYSREF+, SYSREF–). Within the clocking subsystem there is a noiseless aperture delay adjustment (t_AD adjust), a clock duty cycle corrector, and a SYSREF capture block. Figure 7-2 shows the clocking subsystem.

Figure 7-2 ADC12DL3200 Clocking Subsystem

The device clock is used as the sampling clock for the ADC core as well as the clocking for the digital processing and LVDS outputs. Use a low-noise (low jitter) device clock to maintain high signal-to-noise ratio (SNR) within the ADC. In dual-channel mode, the analog input signal for each input is sampled on the rising edge of the device clock. In single-channel mode, both the rising and falling edges of the device clock are used to capture the analog signal to reduce the maximum clock rate required by the ADC. A noiseless aperture delay adjustment (t_AD adjust) allows the sampling instance of the ADC to be shifted in fine steps in order to synchronize multiple ADC12DL3200 devices or to fine-tune system latency. Duty cycle correction is implemented in the ADC12DL3200 to ease the requirements on the external device clock while maintaining high performance. Table 7-3 summarizes the device clock interface in dual-channel mode and single-channel mode.

Table 7-3 Device Clock versus Mode of Operation

MODE OF OPERATION	SAMPLING RATE VS f_CLK	SAMPLING INSTANT
Dual-channel mode	1 × f_CLK	Rising edge
Single-channel mode	2 × f_CLK	Rising and falling edge

SYSREF is a system timing reference used to reset clock dividers and strobe generation within the ADC12DL3200 that is similar to the SYSREF signal used by JESD204B interface devices. SYSREF is used to synchronize multiple ADC12DL3200 devices. SYSREF must be captured by the correct device clock edge in order to achieve repeatable latency and synchronization. The ADC12DL3200 includes SYSREF windowing and automatic SYSREF calibration to ease the requirements on the external clocking circuits and to simplify the synchronization process. SYSREF can be implemented as a single pulse or as a periodic clock. In periodic implementations, SYSREF must be equal to, or an integer division of, the frame clock frequency. Equation 2 can be used to calculate valid SYSREF frequencies.

Equation 2.

where

LDEMUX and LFRAME are register settings
f_CLK is the device clock frequency (CLK±)
n is any positive integer