ZHCSUL6 February 2024 ADC12DL1500 , ADC12DL2500 , ADC12DL500
PRODUCTION DATA
Each register access requires a specific 24-bit pattern at this input. This pattern consists of a read-and-write (R/W) bit, register address, and register value. The data are shifted in MSB first and multi-byte registers are always in little-endian format (least significant byte stored at the lowest address). Setup and hold times with respect to the SCLK must be followed (see the Timing Requirements table).