ZHCSOS8A October 2021 – October 2024 ADC09DJ1300 , ADC09QJ1300 , ADC09SJ1300
PRODUCTION DATA
The FIFO_LANE_ALM register bits indicate if an error has occurred in the synchronizing FIFO between the digital logic block and serializer outputs. If the FIFO pointers are upset due to an undesired clock shift or other single event or incorrect clocking frequencies the FIFO_LANE_ALM bit for the erroneous lane is set to 1. Toggling JESD_EN to 0 and then 1 resets the FIFO logic.