SN74LVTH273

Name: SN74LVTH273
Brand: TI
SKU: SN74LVTH273
Price: 0.302 USD

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具有清零功能的 3.3V ABT 八路 D 類觸發(fā)器

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數(shù)據(jù)表

document-pdfAcrobat SN54LVTH273, SN74LVTH273 數(shù)據(jù)表 (Rev. M) (英語(yǔ))

SN74LVTH273

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數(shù)據(jù)表

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產(chǎn)品詳情

Number of channels

Technology family

LVT

Supply voltage (min) (V)

2.7

Supply voltage (max) (V)

3.6

Input type

TTL-Compatible CMOS

Output type

Push-Pull

Clock frequency (max) (MHz)

150

IOL (max) (mA)

IOH (max) (mA)

-32

Supply current (max) (μA)

5000

Features

Bus-hold, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns)

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Number of channels

Technology family

LVT

Supply voltage (min) (V)

2.7

Supply voltage (max) (V)

3.6

Input type

TTL-Compatible CMOS

Output type

Push-Pull

Clock frequency (max) (MHz)

150

IOL (max) (mA)

IOH (max) (mA)

-32

Supply current (max) (μA)

5000

Features

Bus-hold, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns)

Operating temperature range (°C)

-40 to 85

Rating

Catalog

SOIC (DW)

131.84 mm2 12.8 x 10.3

SOP (NS)

98.28 mm2 12.6 x 7.8

SSOP (DB)

56.16 mm2 7.2 x 7.8

TSSOP (PW)

41.6 mm2 6.5 x 6.4

Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V V_CC)
Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
Support Unregulated Battery Operation Down to 2.7 V
Buffered Clock and Direct-Clear Inputs
Individual Data Input to Each Flip-Flop
I_off Supports Partial-Power-Down-Mode Operation
Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 500 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)

Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V V_CC)
Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
Support Unregulated Battery Operation Down to 2.7 V
Buffered Clock and Direct-Clear Inputs
Individual Data Input to Each Flip-Flop
I_off Supports Partial-Power-Down-Mode Operation
Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 500 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)

These octal D-type flip-flops are designed specifically for low-voltage (3.3-V) V_CC operation, but with the capability to provide a TTL interface to a 5-V system environment.

The ’LVTH273 devices are positive-edge-triggered flip-flops with a direct-clear input. Information at the data (D) inputs meeting the setup-time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

These devices are fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

These octal D-type flip-flops are designed specifically for low-voltage (3.3-V) V_CC operation, but with the capability to provide a TTL interface to a 5-V system environment.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

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	類型	標(biāo)題		下載最新的英語(yǔ)版本		日期
*	數(shù)據(jù)表	SN54LVTH273, SN74LVTH273 數(shù)據(jù)表 (Rev. M)				2003年 10月 13日
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	應(yīng)用手冊(cè)	An Overview of Bus-Hold Circuit and the Applications (Rev. B)				2018年 9月 17日
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