SN74LVTH125

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具有總線保持、TTL 兼容型 CMOS 輸入和三態(tài)輸出的 4 通道、2.7V 至 3.6V 緩沖器

產(chǎn)品詳情

Technology family LVT Supply voltage (min) (V) 2.7 Supply voltage (max) (V) 3.6 Number of channels 4 IOL (max) (mA) 64 Supply current (max) (μA) 7000 IOH (max) (mA) -32 Input type TTL-Compatible CMOS Output type 3-State Features Bus-hold, Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns) Rating Catalog Operating temperature range (°C) -40 to 85
Technology family LVT Supply voltage (min) (V) 2.7 Supply voltage (max) (V) 3.6 Number of channels 4 IOL (max) (mA) 64 Supply current (max) (μA) 7000 IOH (max) (mA) -32 Input type TTL-Compatible CMOS Output type 3-State Features Bus-hold, Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns) Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (D) 14 51.9 mm2 8.65 x 6 SOP (NS) 14 79.56 mm2 10.2 x 7.8 SSOP (DB) 14 48.36 mm2 6.2 x 7.8 TSSOP (PW) 14 32 mm2 5 x 6.4 TVSOP (DGV) 14 23.04 mm2 3.6 x 6.4 VQFN (RGY) 14 12.25 mm2 3.5 x 3.5
  • Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
  • Support Unregulated Battery Operation Down to 2.7 V
  • Typical VOLP (Output Ground Bounce)
       <0.8 V at VCC = 3.3 V, TA = 25°C
  • Ioff and Power-Up 3-State Support Hot Insertion
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Latch-Up Performance Exceeds 500 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
  • Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
  • Support Unregulated Battery Operation Down to 2.7 V
  • Typical VOLP (Output Ground Bounce)
       <0.8 V at VCC = 3.3 V, TA = 25°C
  • Ioff and Power-Up 3-State Support Hot Insertion
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Latch-Up Performance Exceeds 500 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)

These bus buffers are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.

The ’LVTH125 devices feature independent line drivers with 3-state outputs. Each output is in the high-impedance state when the associated output-enable (OE)\ input is high.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

These bus buffers are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.

The ’LVTH125 devices feature independent line drivers with 3-state outputs. Each output is in the high-impedance state when the associated output-enable (OE)\ input is high.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.
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類型 標(biāo)題 下載最新的英語(yǔ)版本 日期
* 數(shù)據(jù)表 SN54LVTH125, SN74LVTH125 數(shù)據(jù)表 (Rev. I) 2003年 10月 13日
應(yīng)用手冊(cè) 慢速或浮點(diǎn) CMOS 輸入的影響 (Rev. E) PDF | HTML 英語(yǔ)版 (Rev.E) 2025年 3月 26日
應(yīng)用手冊(cè) An Overview of Bus-Hold Circuit and the Applications (Rev. B) 2018年 9月 17日
選擇指南 Logic Guide (Rev. AB) 2017年 6月 12日
應(yīng)用手冊(cè) Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
選擇指南 邏輯器件指南 2014 (Rev. AA) 最新英語(yǔ)版本 (Rev.AC) PDF | HTML 2014年 11月 17日
選擇指南 《高級(jí)總線接口邏輯器件選擇指南》 英語(yǔ)版 2010年 7月 7日
用戶指南 LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
應(yīng)用手冊(cè) Simultaneous-Switching Performance of TI Logic Devices (Rev. B) 2005年 2月 23日
應(yīng)用手冊(cè) Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
應(yīng)用手冊(cè) TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
應(yīng)用手冊(cè) 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002年 5月 22日
應(yīng)用手冊(cè) Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 2002年 5月 10日
應(yīng)用手冊(cè) LVT-to-LVTH Conversion 1998年 12月 8日
應(yīng)用手冊(cè) LVT Family Characteristics (Rev. A) 1998年 3月 1日
應(yīng)用手冊(cè) Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997年 8月 1日
應(yīng)用手冊(cè) Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日
應(yīng)用手冊(cè) Live Insertion 1996年 10月 1日
應(yīng)用手冊(cè) Understanding Advanced Bus-Interface Products Design Guide 1996年 5月 1日
選擇指南 Logic Guide (Rev. AC) PDF | HTML 1994年 6月 1日

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14-24-LOGIC-EVM 評(píng)估模塊 (EVM) 設(shè)計(jì)用于支持采用 14 引腳至 24 引腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯器件。

用戶指南: PDF | HTML
英語(yǔ)版 (Rev.B): PDF | HTML
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14-24-EVM 是一款靈活的評(píng)估模塊 (EVM)，旨在支持具有 14 引腳至 24 引腳 BQA、BQB、RGY、RSV、RJW 或 RHL 封裝的任何邏輯或轉(zhuǎn)換器件。

用戶指南: PDF | HTML
英語(yǔ)版 (Rev.A): PDF | HTML
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仿真模型

SN74LVTH125 Behavioral SPICE Model

SCBM115.ZIP (7 KB) - PSpice Model
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仿真模型

SN74LVTH125 IBIS Model

SCEM176.ZIP (16 KB) - IBIS Model
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封裝 引腳 CAD 符號(hào)、封裝和 3D 模型
SOIC (D) 14 Ultra Librarian
SOP (NS) 14 Ultra Librarian
SSOP (DB) 14 Ultra Librarian
TSSOP (PW) 14 Ultra Librarian
TVSOP (DGV) 14 Ultra Librarian
VQFN (RGY) 14 Ultra Librarian

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包含信息：
  • RoHS
  • REACH
  • 器件標(biāo)識(shí)
  • 引腳鍍層/焊球材料
  • MSL 等級(jí)/回流焊峰值溫度
  • MTBF/時(shí)基故障估算
  • 材料成分
  • 鑒定摘要
  • 持續(xù)可靠性監(jiān)測(cè)
包含信息：
  • 制造廠地點(diǎn)
  • 封裝廠地點(diǎn)

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