SN74LVC821A

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具有三態(tài)輸出的 10 位總線接口觸發(fā)器

產(chǎn)品詳情

Number of channels 10 Technology family LVC Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 3.6 Input type Standard CMOS Output type 3-State Clock frequency (max) (MHz) 150 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (μA) 10 Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
Number of channels 10 Technology family LVC Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 3.6 Input type Standard CMOS Output type 3-State Clock frequency (max) (MHz) 150 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (μA) 10 Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
SOIC (DW) 24 159.65 mm2 15.5 x 10.3 SSOP (DB) 24 63.96 mm2 8.2 x 7.8 TSSOP (PW) 24 49.92 mm2 7.8 x 6.4 TVSOP (DGV) 24 32 mm2 5 x 6.4
  • Operates From 1.65 V to 3.6 V
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 7.3 ns at 3.3 V
  • Typical VOLP (Output Ground Bounce)
       <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
       >2 V at VCC = 3.3 V, TA = 25°C
  • Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC)
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
  • Operates From 1.65 V to 3.6 V
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 7.3 ns at 3.3 V
  • Typical VOLP (Output Ground Bounce)
       <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
       >2 V at VCC = 3.3 V, TA = 25°C
  • Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC)
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)

This 10-bit bus-interface flip-flop is designed for 1.65-V to 3.6-V VCC operation.

The SN74LVC821A features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers.

The ten flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs.

A buffered output-enable (OE)\ input can be used to place the ten outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

OE\ does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This 10-bit bus-interface flip-flop is designed for 1.65-V to 3.6-V VCC operation.

The SN74LVC821A features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers.

The ten flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs.

A buffered output-enable (OE)\ input can be used to place the ten outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

OE\ does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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類型 標(biāo)題 下載最新的英語(yǔ)版本 日期
* 數(shù)據(jù)表 SN74LVC821A 數(shù)據(jù)表 (Rev. J) 2003年 7月 31日
應(yīng)用手冊(cè) 慢速或浮點(diǎn) CMOS 輸入的影響 (Rev. E) PDF | HTML 英語(yǔ)版 (Rev.E) 2025年 3月 26日
應(yīng)用手冊(cè) Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022年 12月 15日
選擇指南 Little Logic Guide 2018 (Rev. G) 2018年 7月 6日
選擇指南 Logic Guide (Rev. AB) 2017年 6月 12日
應(yīng)用手冊(cè) How to Select Little Logic (Rev. A) 2016年 7月 26日
應(yīng)用手冊(cè) Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
選擇指南 邏輯器件指南 2014 (Rev. AA) 最新英語(yǔ)版本 (Rev.AC) PDF | HTML 2014年 11月 17日
選擇指南 小尺寸邏輯器件指南 (Rev. E) 最新英語(yǔ)版本 (Rev.G) 2012年 7月 16日
用戶指南 LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
應(yīng)用手冊(cè) CMOS 非緩沖反向器在振蕩器電路中的使用 英語(yǔ)版 2006年 3月 23日
應(yīng)用手冊(cè) 選擇正確的電平轉(zhuǎn)換解決方案 (Rev. A) 英語(yǔ)版 (Rev.A) 2006年 3月 23日
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用戶指南 Signal Switch Data Book (Rev. A) 2003年 11月 14日
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應(yīng)用手冊(cè) Texas Instruments Little Logic Application Report 2002年 11月 1日
應(yīng)用手冊(cè) TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
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應(yīng)用手冊(cè) Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 2002年 5月 10日
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應(yīng)用手冊(cè) Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 1997年 12月 1日
應(yīng)用手冊(cè) Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997年 8月 1日
應(yīng)用手冊(cè) CMOS Power Consumption and CPD Calculation (Rev. B) 1997年 6月 1日
應(yīng)用手冊(cè) LVC Characterization Information 1996年 12月 1日
應(yīng)用手冊(cè) Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日
應(yīng)用手冊(cè) Live Insertion 1996年 10月 1日
設(shè)計(jì)指南 Low-Voltage Logic (LVC) Designer's Guide 1996年 9月 1日
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選擇指南 Logic Guide (Rev. AC) PDF | HTML 1994年 6月 1日

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用戶指南: PDF | HTML
英語(yǔ)版 (Rev.B): PDF | HTML
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仿真模型

SN74LVC821A IBIS Model

SCAM049.ZIP (41 KB) - IBIS Model
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封裝 引腳 CAD 符號(hào)、封裝和 3D 模型
SOIC (DW) 24 Ultra Librarian
SSOP (DB) 24 Ultra Librarian
TSSOP (PW) 24 Ultra Librarian
TVSOP (DGV) 24 Ultra Librarian

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  • 引腳鍍層/焊球材料
  • MSL 等級(jí)/回流焊峰值溫度
  • MTBF/時(shí)基故障估算
  • 材料成分
  • 鑒定摘要
  • 持續(xù)可靠性監(jiān)測(cè)
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