SN74F74
- Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs
These devices contain two independent positive-edge-triggered
D-type flip-flops. A low level at the preset (
) or clear (
) inputs sets or resets the outputs
regardless of the levels of the other inputs. When
and
are inactive (high), data at the
data (D) input meeting the setup time requirements is transferred to
the outputs on the positive-going edge of the clock pulse. Clock
triggering occurs at a voltage level and is not directly related to
the rise time of the clock pulse. Following the hold-time interval,
data at the D input may be changed without affecting the levels at
the outputs.
The SN54F74 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F74 is characterized for operation from 0°C to 70°C.
The output levels are not guaranteed to meet the minimum
levels for VOH. Furthermore, this configuration is
nonstable; that is, it will not persist when
or
returns to its inactive (high) level.
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技術(shù)文檔
| 類型 | 標(biāo)題 | 下載最新的英語版本 | 日期 | |||
|---|---|---|---|---|---|---|
| * | 數(shù)據(jù)表 | Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear And Preset 數(shù)據(jù)表 (Rev. A) | 1993年 10月 1日 |
訂購和質(zhì)量
- RoHS
- REACH
- 器件標(biāo)識
- 引腳鍍層/焊球材料
- MSL 等級/回流焊峰值溫度
- MTBF/時基故障估算
- 材料成分
- 鑒定摘要
- 持續(xù)可靠性監(jiān)測
- 制造廠地點
- 封裝廠地點