SN74ALS165

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并聯(lián)負(fù)載 8 位串行移位寄存器

產(chǎn)品詳情

Configuration Parallel-in, Serial-out Bits (#) 8 Technology family ALS Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type Bipolar Output type Push-Pull Clock frequency (MHz) 45 IOL (max) (mA) 8 IOH (max) (mA) -0.4 Supply current (max) (μA) 24000 Features High speed (tpd 10-50ns) Operating temperature range (°C) 0 to 70 Rating Catalog
Configuration Parallel-in, Serial-out Bits (#) 8 Technology family ALS Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type Bipolar Output type Push-Pull Clock frequency (MHz) 45 IOL (max) (mA) 8 IOH (max) (mA) -0.4 Supply current (max) (μA) 24000 Features High speed (tpd 10-50ns) Operating temperature range (°C) 0 to 70 Rating Catalog
PDIP (N) 16 181.42 mm2 19.3 x 9.4 SOIC (D) 16 59.4 mm2 9.9 x 6
  • Complementary Outputs
  • Direct Overriding Load (Data) Inputs
  • Gated Clock Inputs
  • Parallel-to-Serial Data Conversion
  • Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
  • Complementary Outputs
  • Direct Overriding Load (Data) Inputs
  • Gated Clock Inputs
  • Parallel-to-Serial Data Conversion
  • Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

The 'ALS165 are parallel-load 8-bit serial shift registers that, when clocked, shift the data toward serial (QH and Q\H) outputs. Parallel-in access to each stage is provided by eight individual direct data (A-H) inputs that are enabled by a low level at the shift/load (SH/LD\) input. The 'ALS165 have a clock-inhibit function and complemented serial outputs.

Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD\ is held high and the clock inhibit (CLK INH) input is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a low-to-high transition of CLK INH also accomplishes clocking, CLK INH should be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/LD\ is held high. The parallel inputs to the register are enabled while SH/LD\ is low independently of the levels of the CLK, CLK INH, or serial (SER) inputs.

The SN54ALS165 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS165 is characterized for operation from 0°C to 70°C.

The 'ALS165 are parallel-load 8-bit serial shift registers that, when clocked, shift the data toward serial (QH and Q\H) outputs. Parallel-in access to each stage is provided by eight individual direct data (A-H) inputs that are enabled by a low level at the shift/load (SH/LD\) input. The 'ALS165 have a clock-inhibit function and complemented serial outputs.

Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD\ is held high and the clock inhibit (CLK INH) input is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a low-to-high transition of CLK INH also accomplishes clocking, CLK INH should be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/LD\ is held high. The parallel inputs to the register are enabled while SH/LD\ is low independently of the levels of the CLK, CLK INH, or serial (SER) inputs.

The SN54ALS165 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS165 is characterized for operation from 0°C to 70°C.

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類型 標(biāo)題 下載最新的英語版本 日期
* 數(shù)據(jù)表 Parallel-Load 8-Bit Registers 數(shù)據(jù)表 (Rev. B) 1994年 12月 1日

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