SN65LVDS32
- Meet or Exceed the Requirements of ANSI
TIA/EIA-644 Standard - Operate With a Single 3.3-V Supply
- Designed for Signaling Rates of up to
150 Mbps - Differential Input Thresholds ±100 mV Max
- Typical Propagation Delay Time of 2.1 ns
- Power Dissipation 60 mW Typical Per
Receiver at Maximum Data Rate - Bus-Terminal ESD Protection Exceeds 8 kV
- Low-Voltage TTL (LVTTL) Logic Output
Levels - Pin Compatible With AM26LS32, MC3486,
and μA9637 - Open-Circuit Fail-Safe
- Cold Sparing for Space and High-Reliability
Applications Requiring Redundancy
The SN55LVDS32, SN65LVDS32, SN65LVDS3486, and SN65LVDS9637 devices are differential line receivers that implement the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3.3-V supply rail. Any of the differential receivers provides a valid logical output state with a ±100-mV differential input voltage within the input common-mode voltage range. The input common-mode voltage range allows 1 V of ground potential difference between two LVDS nodes.
The intended application of these devices and signaling technique is both point-to-point and multidrop (one driver and multiple receivers) data transmission over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer depends on the attenuation characteristics of the media and the noise coupling to the environment.
The SN65LVDS32, SN65LVDS3486, and SN65LVDS9637 devices are characterized for operation from –40°C to 85°C. The SN55LVDS32 device is characterized for operation from –55°C to 125°C.
技術(shù)文檔
| 類型 | 標題 | 下載最新的英語版本 | 日期 | |||
|---|---|---|---|---|---|---|
| * | 數(shù)據(jù)表 | SNx5LVDS32, SN65LVDS3486, SN65LVDS9637 High-Speed Differential Line Receivers 數(shù)據(jù)表 (Rev. R) | 2014年 8月 6日 | |||
| 應(yīng)用簡報 | LVDS to Improve EMC in Motor Drives | 2018年 9月 27日 | ||||
| 應(yīng)用簡報 | How Far, How Fast Can You Operate LVDS Drivers and Receivers? | 2018年 8月 3日 | ||||
| 應(yīng)用簡報 | How to Terminate LVDS Connections with DC and AC Coupling | 2018年 5月 16日 | ||||
| 應(yīng)用手冊 | LVDS Multidrop Connections (Rev. A) | 2002年 2月 11日 | ||||
| 應(yīng)用手冊 | Performance of LVDS with Different Cables (Rev. B) | 2002年 2月 11日 | ||||
| 應(yīng)用手冊 | An Overview of LVDS Technology | 1998年 10月 5日 |
設(shè)計和開發(fā)
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SN65LVDS31-32EVM — 適用于 SNx5LVDS31 和 SNx5LVDS32 的 SN65LVDS31-32EVM 評估模塊
The SN65LVDS31-32EVM evaluation moduel (EVM) includes the SV65LVDS31 quad driver and the SN65LVDS32 quad receiver. The SN65LVDS31 device is a TIA/EIA-644 standard-compliant LVDS driver. The SN65LVDS32 device is a TIA/EIA-644 standard-compliant receiver that has a passive open-circuit failsafe (...)
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| 封裝 | 引腳 | CAD 符號、封裝和 3D 模型 |
|---|---|---|
| SOIC (D) | 16 | Ultra Librarian |
| SOP (NS) | 16 | Ultra Librarian |
| TSSOP (PW) | 16 | Ultra Librarian |
訂購和質(zhì)量
- RoHS
- REACH
- 器件標識
- 引腳鍍層/焊球材料
- MSL 等級/回流焊峰值溫度
- MTBF/時基故障估算
- 材料成分
- 鑒定摘要
- 持續(xù)可靠性監(jiān)測
- 制造廠地點
- 封裝廠地點
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