主頁 接口 LVDS、M-LVDS 和 PECL IC

SN65LVDS100

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2Gbps LVDS、LVPECL 和 CML 轉(zhuǎn) LVDS 緩沖器、中繼器和轉(zhuǎn)換器

產(chǎn)品詳情

Function Repeater, Translator Protocols CML, LVDS, LVPECL Number of transmitters 1 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (Mbps) 2000 Input signal CML, LVDS, LVPECL Output signal LVDS Rating Catalog Operating temperature range (°C) -40 to 85
Function Repeater, Translator Protocols CML, LVDS, LVPECL Number of transmitters 1 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (Mbps) 2000 Input signal CML, LVDS, LVPECL Output signal LVDS Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (D) 8 29.4 mm2 4.9 x 6 VSSOP (DGK) 8 14.7 mm2 3 x 4.9
  • Designed for Signaling Rates ≥ 2 Gbps
  • Total Jitter < 65 ps
  • Low-Power Alternative for the MC100EP16
  • Low 100-ps (Maximum) Part-to-Part Skew
  • 25 mV of Receiver Input Threshold Hysteresis
    Over 0-V to 4-V Input Voltage Range
  • Inputs Electrically Compatible With LVPECL,
    CML, and LVDS Signal Levels
  • 3.3-V Supply Operation
  • LVDT Integrates 110-Ω Terminating Resistor
  • Offered in SOIC and MSOP
  • Designed for Signaling Rates ≥ 2 Gbps
  • Total Jitter < 65 ps
  • Low-Power Alternative for the MC100EP16
  • Low 100-ps (Maximum) Part-to-Part Skew
  • 25 mV of Receiver Input Threshold Hysteresis
    Over 0-V to 4-V Input Voltage Range
  • Inputs Electrically Compatible With LVPECL,
    CML, and LVDS Signal Levels
  • 3.3-V Supply Operation
  • LVDT Integrates 110-Ω Terminating Resistor
  • Offered in SOIC and MSOP

The SN65LVDS100, SN65LVDT100, SN65LVDS101, and SN65LVDT101 are high-speed differential receivers and drivers connected as repeaters. The receiver accepts low-voltage differential signaling (LVDS), positive-emitter-coupled logic (PECL), or current-mode logic (CML) input signals at rates up to 2 Gbps and repeats it as either an LVDS or PECL output signal. The signal path through the device is differential for low radiated emissions and minimal added jitter.

The outputs of the SN65LVDS100 and SN65LVDT100 are LVDS levels as defined by TIA/EIA-644-A. The outputs of the SN65LVDS101 and SN65LVDT101 are compatible with 3.3-V PECL levels. Both drive differential transmission lines with nominally 100-Ω characteristic impedance.

The SN65LVDT100 and SN65LVDT101 include a 110-Ω differential line termination resistor for less board space, fewer components, and the shortest stub length possible. They do not include the VBB voltage reference found in the SN65LVDS100 and SN65LVDS101. VBB provides a voltage reference of typically 1.35 V below VCC for use in receiving single-ended input signals and is particularly useful with single-ended 3.3-V PECL inputs. When VBB is not used, it should be unconnected or open.

All devices are characterized for operation from –40°C to 85°C.

The SN65LVDS100, SN65LVDT100, SN65LVDS101, and SN65LVDT101 are high-speed differential receivers and drivers connected as repeaters. The receiver accepts low-voltage differential signaling (LVDS), positive-emitter-coupled logic (PECL), or current-mode logic (CML) input signals at rates up to 2 Gbps and repeats it as either an LVDS or PECL output signal. The signal path through the device is differential for low radiated emissions and minimal added jitter.

The outputs of the SN65LVDS100 and SN65LVDT100 are LVDS levels as defined by TIA/EIA-644-A. The outputs of the SN65LVDS101 and SN65LVDT101 are compatible with 3.3-V PECL levels. Both drive differential transmission lines with nominally 100-Ω characteristic impedance.

The SN65LVDT100 and SN65LVDT101 include a 110-Ω differential line termination resistor for less board space, fewer components, and the shortest stub length possible. They do not include the VBB voltage reference found in the SN65LVDS100 and SN65LVDS101. VBB provides a voltage reference of typically 1.35 V below VCC for use in receiving single-ended input signals and is particularly useful with single-ended 3.3-V PECL inputs. When VBB is not used, it should be unconnected or open.

All devices are characterized for operation from –40°C to 85°C.
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類型 標(biāo)題 下載最新的英語版本 日期
* 數(shù)據(jù)表 SN65LVDx10x Differential Translator/Repeater 數(shù)據(jù)表 (Rev. E) PDF | HTML 2015年 7月 20日
應(yīng)用簡報 How to Use a 3.3-V LVDS Buffer as a Low-Voltage LVDS Driver 2019年 1月 9日
應(yīng)用手冊 Signaling Rate vs. Distance for Differential Buffers 2010年 1月 26日
應(yīng)用手冊 AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C) 2007年 10月 17日
應(yīng)用手冊 DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CML 2003年 2月 19日
EVM 用戶指南 2-GBPS Differential Repeater EVM (Rev. A) 2002年 11月 11日
更多文獻資料 HPL EVM Program 2002年 8月 29日
EVM 用戶指南 2-GBPS Differential Repeater EVM 2002年 8月 8日

設(shè)計和開發(fā)

如需其他信息或資源，請點擊以下任一標(biāo)題進入詳情頁面查看（如有）。

評估板

SN65CML100EVM — SN65CML100 評估模塊]]

The EVM allows evaluation of operation of theSN65LVDS100/101 or SN65CML100 high-speed differential translators/repeaters.  Differential input signals (LVDS, LVPECL, CML, etc.) can be applied and the device output can beobserved across on board terminations, or via direct connection to 50-ohm (...)

用戶指南: PDF
TI.com 上無現(xiàn)貨
評估板

SN65LVDS100EVM — SN65LVDS100 評估模塊

The EVM allows evaluation of operation of the SN65LVDS100/101 or SN65CML100 high-speed differential translators/repeaters.  Differential input signals (LVDS, LVPECL, CML, etc.) can be applied and the device output can be observed across on board terminations, or via direct connection to (...)

用戶指南: PDF
TI.com 上無現(xiàn)貨
仿真模型

SN65LVDS100 IBIS Model

SLLC124.ZIP (3 KB) - IBIS Model
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模擬工具

PSPICE-FOR-TI — PSpice? for TI 設(shè)計和仿真工具

PSpice? for TI 可提供幫助評估模擬電路功能的設(shè)計和仿真環(huán)境。此功能齊全的設(shè)計和仿真套件使用 Cadence? 的模擬分析引擎。PSpice for TI 可免費使用，包括業(yè)內(nèi)超大的模型庫之一，涵蓋我們的模擬和電源產(chǎn)品系列以及精選的模擬行為模型。

借助?PSpice for TI 的設(shè)計和仿真環(huán)境及其內(nèi)置的模型庫，您可對復(fù)雜的混合信號設(shè)計進行仿真。創(chuàng)建完整的終端設(shè)備設(shè)計和原型解決方案，然后再進行布局和制造，可縮短產(chǎn)品上市時間并降低開發(fā)成本。?

在?PSpice for TI 設(shè)計和仿真工具中，您可以搜索 TI (...)
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模擬工具

TINA-TI — 基于 SPICE 的模擬仿真程序

TINA-TI 提供了 SPICE 所有的傳統(tǒng)直流、瞬態(tài)和頻域分析以及更多。TINA 具有廣泛的后處理功能，允許您按照希望的方式設(shè)置結(jié)果的格式。虛擬儀器允許您選擇輸入波形、探針電路節(jié)點電壓和波形。TINA 的原理圖捕獲非常直觀 - 真正的“快速入門”。

TINA-TI 安裝需要大約 500MB。直接安裝，如果想卸載也很容易。我們相信您肯定會愛不釋手。

TINA 是德州儀器 (TI) 專有的 DesignSoft 產(chǎn)品。該免費版本具有完整的功能，但不支持完整版 TINA 所提供的某些其他功能。

如需獲取可用 TINA-TI 模型的完整列表，請參閱：SpiceRack - 完整列表 

需要 HSpice (...)

用戶指南: PDF
英語版 (Rev.A): PDF
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參考設(shè)計

PMP9767 — 面向 12 位、500MSPS ADC 的高效、無 LDO 電源參考設(shè)計

數(shù)據(jù)轉(zhuǎn)換器的電子性能取決于其電源電壓的穩(wěn)定度。線性穩(wěn)壓器 (LDO) 很常用，但其效率低且功率損失大，因此不適合便攜式應(yīng)用。

然而，使用諸如 TPS62231 和 TPS62237 等開關(guān)模式電源 (SMPS) 是一種經(jīng)濟實惠且高效的電源解決方案。此類解決方案不會使 12 位 ADS540x 系列的模數(shù)轉(zhuǎn)換器 (ADC) 出現(xiàn)性能降級，且不會浪費過多功率。測試報告顯示了兩個電源之間的信噪比 (SNR) 和無偽波動態(tài)范圍 (SFDR) 比較情況，證明它們的性能相同。

測試報告: PDF
原理圖: PDF
參考設(shè)計

TIDA-00074 — 寬帶射頻-數(shù)字復(fù)雜接收器反饋信號鏈

這是一個寬帶復(fù)雜接收器參考設(shè)計和評估平臺，非常適合用作發(fā)送器數(shù)字預(yù)失真的反饋接收器。EVM 信號鏈非常適合高中頻 (IF) 復(fù)雜反饋應(yīng)用，其中包含一個復(fù)雜解調(diào)器、TI 的 LMH6521 雙通道 DVGA 和 ADS5402 12 位 800-MSPS 雙通道 ADC。通過修改板載濾波器組件，可針對各種頻率規(guī)劃配置該信號鏈。EVM 還包括 TI 的 LMK04808 雙 PLL 時鐘抖動清除器和發(fā)生器，用以提供板載低噪音計時解決方案。可通過 GUI 或通過具有 FPGA 的高速連接器控制 LMH6521 DVGA 增益。
設(shè)計指南: PDF
原理圖: PDF
封裝 引腳 CAD 符號、封裝和 3D 模型
SOIC (D) 8 Ultra Librarian
VSSOP (DGK) 8 Ultra Librarian

訂購和質(zhì)量

包含信息：
  • RoHS
  • REACH
  • 器件標(biāo)識
  • 引腳鍍層/焊球材料
  • MSL 等級/回流焊峰值溫度
  • MTBF/時基故障估算
  • 材料成分
  • 鑒定摘要
  • 持續(xù)可靠性監(jiān)測
包含信息：
  • 制造廠地點
  • 封裝廠地點

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