主頁(yè) 接口 LVDS、M-LVDS 和 PECL IC

SN65CML100

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1.5Gbps LVDS/LVPECL/CML 至 CML 轉(zhuǎn)換器/中繼器

產(chǎn)品詳情

Function Repeater, Translator Protocols CML, LVDS, LVPECL Number of transmitters 1 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (Mbps) 1500 Input signal CML, LVDS, LVPECL Output signal CML Rating Catalog Operating temperature range (°C) -40 to 85
Function Repeater, Translator Protocols CML, LVDS, LVPECL Number of transmitters 1 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (Mbps) 1500 Input signal CML, LVDS, LVPECL Output signal CML Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (D) 8 29.4 mm2 4.9 x 6 VSSOP (DGK) 8 14.7 mm2 3 x 4.9
  • Provides Level Translation From LVDS or LVPECL to CML, Repeating From CML to CML
  • Signaling Rates1 up to 1.5 Gbps
  • CML Compatible Output Directly Drives Devices With 3.3-V, 2.5-V, or 1.8-V Supplies
  • Total Jitter < 70 ps
  • Low 100 ps (Max) Part-To-Part Skew
  • Wide Common-Mode Receiver Capability Allows Direct Coupling of Input Signals
  • 25 mV of Receiver Input Threshold Hysteresis Over 0-V to 4-V Common-Mode Range
  • Propagation Delay Times, 800 ps Maximum
  • 3.3-V Supply Operation
  • Available in SOIC and MSOP Packages
  • APPLICATIONS
    • Level Translation
    • 622-MHz Central Office Clock Distribution
    • High-Speed Network Routing
    • Wireless Basestations
    • Low Jitter Clock Repeater

1 The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
  • Provides Level Translation From LVDS or LVPECL to CML, Repeating From CML to CML
  • Signaling Rates1 up to 1.5 Gbps
  • CML Compatible Output Directly Drives Devices With 3.3-V, 2.5-V, or 1.8-V Supplies
  • Total Jitter < 70 ps
  • Low 100 ps (Max) Part-To-Part Skew
  • Wide Common-Mode Receiver Capability Allows Direct Coupling of Input Signals
  • 25 mV of Receiver Input Threshold Hysteresis Over 0-V to 4-V Common-Mode Range
  • Propagation Delay Times, 800 ps Maximum
  • 3.3-V Supply Operation
  • Available in SOIC and MSOP Packages
  • APPLICATIONS
    • Level Translation
    • 622-MHz Central Office Clock Distribution
    • High-Speed Network Routing
    • Wireless Basestations
    • Low Jitter Clock Repeater

1 The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).

This high-speed translator/repeater is designed for signaling rates up to 1.5 Gbps to support various high-speed network routing applications. The driver output is compatible with current-mode logic (CML) levels, and directly drives 50- loads connected to 1.8-V, 2.5-V, or 3.3-V nominal supplies. The capability for direct connection to the loads may eliminate the need for coupling capacitors. The receiver input is compatible with LVDS (TIA/EIA–644), LVPECL, and CML signaling levels. The receiver tolerates a wide common-mode voltage range, and may also be directly coupled to the signal source. The internal data path from input to output is fully differential for low noise generation and low pulse-width distortion.

The VBB pin is an internally generated voltage supply to allow operation with a single-ended LVPECL input. For single-ended LVPECL input operation, the unused differential input is connected to VBB as a switching reference voltage. When used, decouple VBB with a 0.01-uF capacitor and limit the current sourcing or sinking to 400 uA. When not used, VBB should be left open.

This device is characterized for operation from –40°C to 85°C.

This high-speed translator/repeater is designed for signaling rates up to 1.5 Gbps to support various high-speed network routing applications. The driver output is compatible with current-mode logic (CML) levels, and directly drives 50- loads connected to 1.8-V, 2.5-V, or 3.3-V nominal supplies. The capability for direct connection to the loads may eliminate the need for coupling capacitors. The receiver input is compatible with LVDS (TIA/EIA–644), LVPECL, and CML signaling levels. The receiver tolerates a wide common-mode voltage range, and may also be directly coupled to the signal source. The internal data path from input to output is fully differential for low noise generation and low pulse-width distortion.

The VBB pin is an internally generated voltage supply to allow operation with a single-ended LVPECL input. For single-ended LVPECL input operation, the unused differential input is connected to VBB as a switching reference voltage. When used, decouple VBB with a 0.01-uF capacitor and limit the current sourcing or sinking to 400 uA. When not used, VBB should be left open.

This device is characterized for operation from –40°C to 85°C.
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類型 標(biāo)題 下載最新的英語(yǔ)版本 日期
* 數(shù)據(jù)表 1.5-Gbps LVDS/LVPECL/CML-to-CML Translator/Repeater 數(shù)據(jù)表 2002年 11月 11日
應(yīng)用手冊(cè) Signaling Rate vs. Distance for Differential Buffers 2010年 1月 26日
EVM 用戶指南 2-GBPS Differential Repeater EVM (Rev. A) 2002年 11月 11日

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評(píng)估板

SN65CML100EVM — SN65CML100 評(píng)估模塊]]

The EVM allows evaluation of operation of theSN65LVDS100/101 or SN65CML100 high-speed differential translators/repeaters.  Differential input signals (LVDS, LVPECL, CML, etc.) can be applied and the device output can beobserved across on board terminations, or via direct connection to 50-ohm (...)

用戶指南: PDF
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仿真模型

SN65CML100 IBIS Model

SLLC131.ZIP (3 KB) - IBIS Model
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用戶指南: PDF
英語(yǔ)版 (Rev.A): PDF
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封裝 引腳 CAD 符號(hào)、封裝和 3D 模型
SOIC (D) 8 Ultra Librarian
VSSOP (DGK) 8 Ultra Librarian

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包含信息：
  • RoHS
  • REACH
  • 器件標(biāo)識(shí)
  • 引腳鍍層/焊球材料
  • MSL 等級(jí)/回流焊峰值溫度
  • MTBF/時(shí)基故障估算
  • 材料成分
  • 鑒定摘要
  • 持續(xù)可靠性監(jiān)測(cè)
包含信息：
  • 制造廠地點(diǎn)
  • 封裝廠地點(diǎn)

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