SN54LS73A

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具有清零功能和三態(tài)輸出的雙通道 J-K 觸發(fā)器

產(chǎn)品詳情

Number of channels 2 Technology family LS Supply voltage (min) (V) 4.75 Supply voltage (max) (V) 5.25 Input type TTL Output type Push-Pull Clock frequency (MHz) 30 Supply current (max) (μA) 6000 IOL (max) (mA) -0.4 IOH (max) (mA) 8 Features Clear, High speed (tpd 10-50ns), Negative edge triggered Operating temperature range (°C) -55 to 125 Rating Military
Number of channels 2 Technology family LS Supply voltage (min) (V) 4.75 Supply voltage (max) (V) 5.25 Input type TTL Output type Push-Pull Clock frequency (MHz) 30 Supply current (max) (μA) 6000 IOL (max) (mA) -0.4 IOH (max) (mA) 8 Features Clear, High speed (tpd 10-50ns), Negative edge triggered Operating temperature range (°C) -55 to 125 Rating Military
CDIP (J) 14 130.4652 mm2 19.56 x 6.67 CFP (W) 14 58.023 mm2 9.21 x 6.3
  • Package Options Include Plastic “Small Outline" Packages, Flat Packages, and Plastic and Ceramic DIPs
  • Dependable Texas Instruments Quality and Reliability

 
  • Package Options Include Plastic “Small Outline" Packages, Flat Packages, and Plastic and Ceramic DIPs
  • Dependable Texas Instruments Quality and Reliability

 

The '73, and 'H73, contain two independent J-K flip-flops with individual J-K, clock, and direct clear inputs. The '73, and 'H73, are positive pulse-triggered flip-flops. J-K input is loaded into the master while the clock is high and transferred to the slave on the high-to-low transition. For these devices the J and K inputs must be stable while the clock is high.

The 'LS73A contains two independent negative-edge-triggered flip-flops. The J and K inputs must be stable one setup time prior to the high-to-low clock transition for predictable operation. When the clear is low, it overrides the clock and data inputs forcing the Q output low and the Q\ output high.

The SN5473, SN54H73, and the SN54LS73A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN7473, and the SN74LS73A are characterized for operation from 0°C to 70°C.

 

The '73, and 'H73, contain two independent J-K flip-flops with individual J-K, clock, and direct clear inputs. The '73, and 'H73, are positive pulse-triggered flip-flops. J-K input is loaded into the master while the clock is high and transferred to the slave on the high-to-low transition. For these devices the J and K inputs must be stable while the clock is high.

The 'LS73A contains two independent negative-edge-triggered flip-flops. The J and K inputs must be stable one setup time prior to the high-to-low clock transition for predictable operation. When the clear is low, it overrides the clock and data inputs forcing the Q output low and the Q\ output high.

The SN5473, SN54H73, and the SN54LS73A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN7473, and the SN74LS73A are characterized for operation from 0°C to 70°C.

 
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類型 標題 下載最新的英語版本 日期
* 數(shù)據(jù)表 Dual J-K Flip-Flops With Clear 數(shù)據(jù)表 1988年 3月 1日

訂購和質(zhì)量

包含信息：
  • RoHS
  • REACH
  • 器件標識
  • 引腳鍍層/焊球材料
  • MSL 等級/回流焊峰值溫度
  • MTBF/時基故障估算
  • 材料成分
  • 鑒定摘要
  • 持續(xù)可靠性監(jiān)測
包含信息：
  • 制造廠地點
  • 封裝廠地點

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